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Emulation is called cycle-accurate if the original system's cycle-synchronous behaviour is fully captured; for example, a cycle-accurate emulation of a CPU, executing an instruction, would first present the externally visible effects of what the original CPU would do in the first cycle of executing that instruction, then so on for the second and subsequent cycles.

I am looking for an established name for a weaker property, where a CPU emulator makes sure that overall, each instruction takes the same number of clock cycles to execute, but between those cycles, makes no effort to present each outside-visible effect at the same cycles.

So for example, a real CPU might execute something like MOV $1234, R in 8 cycles, setting the address bus to $1200 in cycle 3, then to $1234 in cycles 4 and 5, then put the value of the R register on the data bus in cycle 6. Now imagine there is an alternative implementation (be it an emulator, a replacement IC, or an FPGA implementation) that executes MOV $1234, R in 8 cycles, by doing nothing for 4, then putting $1234 on the address bus and the value of R on the data bus in cycle 5, and then does nothing for 3 more cycles, would not be cycle-accurate, but it would meet my definition.

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    @Justme yes, but in my example, the address bus (which of course is visible externally, by memory and memory-mapped peripherals) doesn't behave like the real thing cycle-by-cycle. – Cactus Mar 27 at 9:44
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    OK so I misunderstood that part a little. So the implementation would run at exactly correct speed in regard to correct clock cycles per instruction, but for example reads and writes over bus to video and audio chips would happen at wrong clock cycle? If the system is sensitive to that then it can cause issues and the whole system would not be cycle-accurate. – Justme Mar 27 at 11:00
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    there are more therms for this (I do not think there is official one as emulation started mostly as hobby for programmers so no language normalization...) clock-tics,time bursting,cycle count accuracy. see Question about cycle counting accuracy when emulating a CPU – Spektre Mar 27 at 11:23
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    @Raffzahn You’re assuming purely software emulation, but I’m pretty sure that what Cactus has in mind here is things like FPGA-based hardware emulation of older chips, and when you’re doing that, it becomes very important whether your external hardware interfaces behave exactly like the original, approximately like the original, or not at all like the original. I’d argue it’s also on-topic, given that FPGA soft-core systems that would have to care about this type of thing are not uncommon when recreating old hardware (especially old microcomputers). – Austin Hemmelgarn Mar 28 at 2:01
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    @Raffzahn I know my English is rusty ... but my understanding this question is just asking for the name of the term and not about new SW/HW development (that part is just an example of what the term should means). And knowing if emulator have synchronized execution or just clock-tics is very important. As the latter requires a lot of dirty hacks in order to "emulate peripherials" so a lot of SW that directly access specific components might not work (like custom tape loaders and border effects, etc...) on such emulation. – Spektre Mar 28 at 7:57
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I have once read a blog post by the developer of mGBA, which simply uses ‘cycle-count accuracy’ for this property, and seems to imply this is an established term. Looking up this phrase in a search engine seems to weakly corroborate this, as I found a number of other resources where the same term appears:

As I remember, when I first encountered that blog post, I have never seen those terms before, but my rough knowledge of how CPUs work allowed me to correctly guess what they referred to right away when I saw them contrasted with each other. If you do similarly, I think there should be no misunderstandings.

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I have described such systems as “cycle-approximate”. Some research papers, I found in a short search session agree with this terminology.

It is slightly broader than you use it here, and would indicate to me that some portion of the simulator was incomplete, for example cache modeling, prefetchers, or other complex micro-architectural or system/bus level behaviours.

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