Emulation is called cycle-accurate if the original system's cycle-synchronous behaviour is fully captured; for example, a cycle-accurate emulation of a CPU, executing an instruction, would first present the externally visible effects of what the original CPU would do in the first cycle of executing that instruction, then so on for the second and subsequent cycles.
I am looking for an established name for a weaker property, where a CPU emulator makes sure that overall, each instruction takes the same number of clock cycles to execute, but between those cycles, makes no effort to present each outside-visible effect at the same cycles.
So for example, a real CPU might execute something like
MOV $1234, R in 8 cycles, setting the address bus to
$1200 in cycle 3, then to
$1234 in cycles 4 and 5, then put the value of the
R register on the data bus in cycle 6. Now imagine there is an alternative implementation (be it an emulator, a replacement IC, or an FPGA implementation) that executes
MOV $1234, R in 8 cycles, by doing nothing for 4, then putting
$1234 on the address bus and the value of
R on the data bus in cycle 5, and then does nothing for 3 more cycles, would not be cycle-accurate, but it would meet my definition.