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The MC68030 processor is equipped with dual 256-byte instruction and data caches as well as a "burst" mechanism used to quickly load a cache line from RAM or L2 cache controlled by the platform hardware (motherboard).

My question is, when MC68030 encounters a cache miss and initiates a burst access to fill a line in one of the caches, does program execution resume immediately after the first longword is loaded or only after the burst is completed?

One would think that MC68030 would continue execution right after the requisite data is available, but I have encountered a slide from a MIPS presentation at Hot Chips '89 which suggests that MC68030, in contrast to MIPS's R3000, waits until the burst is completed before continuing execution: MC68030 vs R3000

MIPS calls this idea of the execution continuing as a cache line is loaded "instruction streaming." Of course, this slide is from MIPS's presentation, not Motorola's, so we can expect it to be a bit generous toward R3000 and a bit harsh toward its competitors. The presentation calls out MC68030 and 80386 as being less performant than the R3000, and indeed there is a conspicuous lack of labeling or explanation of which competing processors suffer from the extra latency waiting for completion of the burst. MIPS is clear that the R3000 has instruction streaming, but it's not clear whether the aforementioned competitors have it or not.

The more I think about this, the more confused I get. Any pipelined CPU is always fetching instructions in parallel with executing opcodes already fetched. Even the 8088 has a few byte (IIRC) prefetch queue which is always being filled in the absence of data memory references.

Maybe MIPS's claim refers only to data references and the MC68030 is not able to continue execution when doing a burst into the data cache.

Can anyone shed any light on this?

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  • Certainly the processor cannot continue on a read miss until at least the word of interest has been provided, but the diagram seems to indicate that the processor can simply continue during the refill even before any words have arrived. It seems disingenuous. If the desired word were always sent first, then the continuation could start after 1 word has been transferred instead of waiting for the whole line. – Erik Eidt Apr 11 at 18:32
  • Yes, I agree, the diagram is a little bit disingenuous since it suggests that execution can go on before the first longword has been received. Ignoring that though, MC68030 always fetches the piece of data its most interested in first since it doesn't know whether the motherboard will complete the cycle as a burst or as a single transfer. If the chipset can do a burst, it then then increments A[3:2] internally (not on the bus) to fetch the other four longwords in the cache line, with A[3:2] possibly wrapping around back to 00 if the first word requested was not 16-byte-aligned. – Zane Kaminski Apr 11 at 18:43
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According to the official 68030 User Manual, the '030 performs cache burst fills in critical-word-first order specifically to get the execution units running again.

However, accesses to the remaining words in the cache line are delayed until the fill is complete. This includes the second part of misaligned accesses, which need to access two words in the same line.


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