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On the Commodore 64, there is a 12 bit datapath between memory and the VIC II: the ordinary screen data, which is in DRAM, and another 4 bits which comes from another SRAM chip which may be paged into the CPU's address space. This area contains colour information.

It's occurred to me that exactly the same could be done on the ZX Spectrum, so that the ULA, or whatever hardware generates video, could get at both pixel data and attributes quicker. That could mean not needing to slow the CPU down. Or it could mean being able to use a slower DRAM for cheaper. But it would mean needing another 8 bit wide memory. Maybe a couple of 2114s or something.

Is there any ZX Spectrum or clone that works this way?

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  • 4
    It would most definitely need additional RAM chips as well as multiplex hardware, both considerable increasing cost, not exactly what Sinclair, nor any of the clones had in mind.
    – Raffzahn
    Apr 18, 2021 at 18:11
  • 2
    The regular Spectrum fetches video in four-byte chunks, rather than two — in each eight cycle window the contended area provides for one CPU access plus two columns of video data to be read, which are fetched back-to-back. So I guess you could go up to a 32-bit bus before changing too much else in the video generation. Otherwise: the Pentagon is a clone without contended pauses, but I don’t know how it is designed.
    – Tommy
    Apr 18, 2021 at 19:55
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    The only (8bit) machine I know of that did something like that was the belgian DAI Computer. It split its 48K RAM address range in 3 16K areas of which the 2 upper third one were shared with the video generation logic. The video accessed the memory 16bit wise, the CPU (8080A) 8 bit wise. This allowed the machine to have much better graphic resolution than any contemporay machine (335x240 16colours). Apr 19, 2021 at 6:26
  • @Tommy Pentagon simply runs DRAM at 3.5 MHz, cleverly interleaving CPU and video accesses. It is known that Z80 might only sustain 1 memory access per 3 clocks, so out of every 4 accesses per character (at 3.5MHz DRAM access rate) at most two might be consumed by CPU. The other slots per character (minimum 2 of them) are available for video fetches (1 pix byte + 1 attr byte).
    – lvd
    Apr 19, 2021 at 15:44
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    @Tommy yes indeed, there's a simple "scheduler" that gives to the CPU one DRAM access slot per every CPU memory request. During all other 'free' slots the video constantly refetches an infinite sequence of pixel-attr-pixel-attr-etc. bytes, putting results in separate temporary buffers. When a new character (pixel byte + attr byte) is to be displayed, that temporary buffers are copied, respectively, into shift register and attribute buffer, and addresses for subsequent fetches are updated. The CPU request temporarily holds that infinite sequence of fetches for 1 access slot.
    – lvd
    Apr 19, 2021 at 17:58

2 Answers 2

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There is a Spectrum clone, namely ATMTurbo, that uses 16-bit memory bus. However, 16-bitness of memory is only used in extended video modes of the machine, including text mode, 320x200 16bpp mode and 640x200 hires (1 attr byte per 1 pixel byte) modes. In legacy 256x192 ZX mode, only 8 bits of memory bus are used to fetch video.

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I've just discovered a couple of East German clones doing what I describe and having a 16-bit datapath between memory and video generation. This answer is about the ZX Spectrum clone developed at the Technische Hochschule Ilmenau, called GDC 204. This clone originally just disabled the CPU while the picture was being generated, which is about 60% of the time. To compensate for drastically different timing, the GDC 204 originally shipped with a slightly different ROM. This clone gets a mention also on Czech Wikipedia.

But the specimen on the linked page has been hacked and improved. Notably, the CPU runs all the time, even when the picture is being generated. The new timing only incurs a WAIT state if the CPU is writing to graphics memory. It also has an identical ROM to the one sold in the UK.

As mentioned in one of the comments, the idea of a 16-bit datapath for video generation would incur an increased BOM cost, and so would probably not be commonly found on budget machines like ZX clones. But these designs I've found appear to all have been developed at highschools and universities, perhaps as projects where productionization and mass production are not such great concerns. Anyway, on to technical details:

This machine has the 16K ROM from 0000h to 3FFFh, and 64K DRAM from 0000h to FFFFh, of which 48K is usable because of the ROM in the same space. Similar to the Leningrad. But unlike the Leningrad, the CPU is free to read and write to this DRAM and this ROM at its native speed.

Then, additionally, 4000h-57FFh, which is the framebuffer, is backed by three U6516 chips which appear to be East German SRAMs, 2 Kilobytes each.

Also the region 5800h-5AFFh is backed by two U2114's, which are both 1 kilobyte but only 4 bits in each location. It seems the same component as the Color RAM on the Commodore 64. (The page I linked calls it a U214, this is apparently the name used in the GDR).

Whenever the CPU wants to write to these regions, the write goes to the DRAM and to either one of the U6516s or the two U2114s. There is circuitry to assert /WAIT as necessary. But when the CPU wants to read, it reads from the DRAM only, so this memory access is unhindered. Nifty, eh?

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  • Ugly. Looks like the engineers did not properly understand how to work with DRAM (and hopefully to them Z80 contains the most parts of a DRAM controller). One might argue that SRAMs are faster and could be interleaved between CPU and video accesses faster -- at the price of lots of address MUXes, but yet again that clone has /WAITs, no gain here.
    – lvd
    Feb 21 at 19:42
  • @lvd but DRAM is cheaper. The machine has a full 64K of it, but only 7K of SRAM.
    – OmarL
    Feb 22 at 6:28
  • @lvd the original Spectrum design was ugly too. Then people designed better clones that were incompatible because they weren't so ugly. Feb 22 at 8:31
  • @BruceAbbott At least the original Spectrum had CPU waits done in an ingenious way, otherwise the wait pattern accessing video memory there would be much worse. And the Z80 refreshing capabilities were used to the full as Z80 did video DRAM refreshes when ULA did not access it. And still I doubt that 7k of SRAM were cheaper than 16k of DRAM (original Spectum case).
    – lvd
    Feb 22 at 10:29
  • @lvd I'm not clear what you think is disingenuous about the Ilmenau wait states? They have the advantage of applying only to writes, something that cannot be said for the Sinclair design.
    – OmarL
    Feb 22 at 10:38

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