I've just discovered a couple of East German clones doing what I describe and having a 16-bit datapath between memory and video generation. This answer is about the ZX Spectrum clone developed at the Technische Hochschule Ilmenau, called GDC 204. This clone originally just disabled the CPU while the picture was being generated, which is about 60% of the time. To compensate for drastically different timing, the GDC 204 originally shipped with a slightly different ROM. This clone gets a mention also on Czech Wikipedia.
But the specimen on the linked page has been hacked and improved. Notably, the CPU runs all the time, even when the picture is being generated. The new timing only incurs a WAIT state if the CPU is writing to graphics memory. It also has an identical ROM to the one sold in the UK.
As mentioned in one of the comments, the idea of a 16-bit datapath for video generation would incur an increased BOM cost, and so would probably not be commonly found on budget machines like ZX clones. But these designs I've found appear to all have been developed at highschools and universities, perhaps as projects where productionization and mass production are not such great concerns. Anyway, on to technical details:
This machine has the 16K ROM from 0000h to 3FFFh, and 64K DRAM from 0000h to FFFFh, of which 48K is usable because of the ROM in the same space. Similar to the Leningrad. But unlike the Leningrad, the CPU is free to read and write to this DRAM and this ROM at its native speed.
Then, additionally, 4000h-57FFh, which is the framebuffer, is backed by three U6516 chips which appear to be East German SRAMs, 2 Kilobytes each.
Also the region 5800h-5AFFh is backed by two U2114's, which are both 1 kilobyte but only 4 bits in each location. It seems the same component as the Color RAM on the Commodore 64. (The page I linked calls it a U214, this is apparently the name used in the GDR).
Whenever the CPU wants to write to these regions, it writes to the DRAM as normal, but it also writes either to one of the U6516s, or both U2114s. There is circuitry to assert /WAIT as necessary. But when the CPU wants to read, it reads from the DRAM only, so this memory access is unhindered. Nifty, eh?