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Z80 board with a SIO/0. I am struggling to understand how CPU and SIO frequencies are related, if they are at all. SIO/0 datasheet didn't help much.

If I clock both the CPU and the SIO(TX/RX) from a 1.84320Mhz oscillator all works fine. Only issue I've got here is I can only use x16 multiplier on SIO and use 115200 baud. For some reason x64 multiplier with 28800 baud only outputs gibberish. Is there any obvious reasons for this ?

If I clock the CPU and SIO(CLK) at 4Mhz and SIO(TX/RX) 1.84320Mhz. It mostly works (this is my ideal configuration). But it is not as stable as the previous option. Cannot tell if this is due to higher CPU frequency or due to a frequency mismatch. (PIO works just fine at 4Mhz).

Finally if I feed SIO(TX/RX) at 1.84320Mhz and try to single/slow step the CPU it never works, I mean I observe the code being executed successfully but nothing come out of serial port.

Is there any requirement to have a somewhat matching CPU and TX/RX frequencies or are they completely independent. If they are, any ideas why SIO stops working when single stepped ?

Updates as per the comments: Both Z80 CLK and SIO CLK pin are always driven from the same clock, either 1.84320Mhz or 4.00Mhz. Question is about a potential requirement for this clock needing to match RX/TX clocks for the serial interfaces or if those are completely independent.

All ICs are CMOS, Z80 and PIO perfectly support single-stepping or slow frequencies, I am only having this odd problem with SIO.

This is a homebrew board with no special configuration. Z80, EEPROM, RAM, SIO, PIO are pretty much connected to each other as everyone else does.

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  • It might help if you add information about what computer this is about or if it's a homebrew and in case of the later what structure is used.
    – Raffzahn
    Apr 22, 2021 at 9:05
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    I must again say here, that one can't just stop clock of NMOS ICs in order to single-step them. Most of NMOS ICs (including NMOS Z80 CPUs) are using dynamic latches and won't work correctly past the minimum clocking frequency noted in a datasheet.
    – lvd
    Apr 22, 2021 at 13:54
  • @lvd, thank you. Both Z80 and the SIO are CMOS. Z80 (and PIO) fully supports single stepping (or low frequencies), I only have the issue with SIO.
    – Charles
    Apr 23, 2021 at 10:53
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    @Charles You might have mentioned that right in the beginning - together with what data book/sheet you're referring to. It feels a tiny bit like pulling worms.
    – Raffzahn
    Apr 23, 2021 at 12:32

1 Answer 1

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TL;DR

The various issues are due clocking. In part by using 'unconventional' ways of clock handling but as well by simply violating specs.

Main points are

  • SIO (and in fact CPU) are not static designs but dynamic. As such they requite certain clock speeds and relation.

  • Clocking the system at 10 Hz violates a whole bunch of rules

    • Minimum system clock speed for the SIO is 250 kHz
    • System clock needs to be at least 5 times transmission clock
  • Having other chips (PIO, CPU) working that way does not mean all will

  • Some chips may even comply with such a low clock rate even while specified otherwise (CPU should not - then again, you never specified exactly which CPU is use).

  • Some restrictions have been relaxed with the CMOS variants, but not all.

  • The Z80 is a beast.

(The last is a general mantra to be spoken whenever touching a Zilog part, but mandatory for the SIO)

Solution:

Build a more conventional single stepping circuit - like using DMA or WAIT insertion - and the issues should vanish at once.

Beside that:

Do not assume from single data items. Read The Fine Data Sheet. In full and in all details. They are holy scriptures containing the whole meaning of the world (of that chip). Breath it. Skimming is an art reserved for the master - used to show off that they are fallible as well :))


In Detail

Z80 board with a SIO/0. I am struggling to understand how CPU and SIO frequencies are related, if they are at all. SIO/0 datasheet didn't help much.

As the per data sheet Feb 1980, section Timing:

The SIO must have the same clock as the
CPU (same phase and frequency relationship,
not necessarily the same driver).

If I clock the CPU and SIO(CLK) at 4Mhz and SIO(TX/RX) 1.84320Mhz. It mostly works (this is my ideal configuration). But it is not as stable as the previous option. Cannot tell if this is due to higher CPU frequency or due to a frequency mismatch. (PIO works just fine at 4Mhz).

The Z80 SIO is a rather odd beast, even compared to the other Z80 chips, especially due to the clocking constrains. There's a reason that Intel's 8251 and its grandchildren (16550) sold better. Also, there were later (Zilog) chips that could operate on real independent clock (IIRC).

Finally if I feed SIO(TX/RX) at 1.84320Mhz and try to single/slow step the CPU it never works, I mean I observe the code being executed successfully but nothing come out of serial port.

It might also depend on how your single stepping works. If you take away the clock, the SIO simply stops working.

Enlightenment from a comment:

I am not actually single stepping, a Arduino providing clock at about 10hz or so and monitoring buses and signals

There it comes. The SIO is NOT static. Being a device that is clocked anyway, they had no need to make it static. The maximum cycle time for a Z80 SIO by the Feb 1980 data sheet is 4 µs or 0.25 MHz. Everything below 250 kHz is simply out of spec. And while 1.8 MHz might still work fine, 0.00001 MHz will not.

enter image description here (Data Sheet Feb.1980)

Even quite resource-strapped early systems did their single stepping not by clock throttling but with software, bus arbitration (DMA-request) or cycle stretching (wait insertion). Only these methods will guarantee that the CPU and the system at whole will work as specified.

Lately it became kind of a trend among newcomers to use an Arduino or RPi or alike to throttle a classic CPU. Sounds great at first. This may work with some CPUs and some system setups, but it relies heavy on static operation of all components, relation between them and other factors. So, methods relying on many unknown factors to work exactly like it would be best is ... well ... let's just say not a good idea.

Even without knowing your setup, I'd say it's your way of "single stepping". which causes at least some of the issues. You may need to create a way more traditional single-stepping solution. Enjoy it; it's the first step in creating a wonderful front panel.

All ICs are CMOS, Z80 and PIO perfectly support single-stepping or slow frequencies, I am only having this odd problem with SIO.

Err sure they support that use, or do they just seem to work in your setup?

This is a homebrew board with no special configuration. Z80, EEPROM, RAM, SIO, PIO are pretty much connected to each other as everyone else does.

Especially when beginning it is helpful to remember that there is no non-special circuit and 'pretty much' leaves a lot of freedom.

With all the software we're doing (and software like hardware design), we tend to see hardware the same, but in reality, working with physical hardware means being able to bend the fabric of (digital) reality. Up to a point were it's beyond the physics of existence - like here :))

From a further comment:

On SIO datasheet,

It might help if you specify (and optional link) the data sheet you're referring to. Mine are taken of off the Z80 SIO Product Specification sheet of February 1980 on my storage system - should be out there on the net as well.

for TcC (Clock Cycle Time), it gives a minimum but the maximum is DC. I read this as, "clock cycle can take forever"

Well, that gives a clear clue - wrong table you'r looking at. Beside that the page before already defines the minimum clock rate for that chip at 250 kHz, not 10, this one puts in addition transmission clock in relation to system clock. Of course, transmission clock can be as slow as one wants - here noted as infinite - but the Issue is not about transmission clock but system clock (see above) and their relation as seen on the very page cited:

enter image description here

While TxC may be in either state as long as one wants, system clock must be at least five times as high. So for 115 kHz transmission rate system clock must be at least 575 kHz. Clocking at 10 Hz does violate this.

Bottom line: Data sheets are holy scriptures. one has to read each and every letter before starting to preach ... err ... solder, as the true meaning is often hidden in plain sight. But it's always there - at least in later editions :))


For debugging serial it usually helps to select a word format with most relaxed parameters, like maximum stop bits, and checking on the receiving side only for low order bits. That helps cross a few pitfalls to get basic workings.

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    Thanks a lot @Raffzahn, just to clarify I am of course using the same clock for the CLK pins of CPU and SIO. So question was about a need to have a relationship between CLK and TXCA/RXCA inputs or not. I am guessing that these are completely independent aren't they ? If they are it is hard to explain single step not working (I am not actually single stepping, a Arduino providing clock at about 10hz or so and monitoring busses and signals. I can see correct instructions being executed to output correct values to SIO but it seems to stop producing output at TXDA for some reason.
    – Charles
    Apr 22, 2021 at 12:46
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    @Charles Please put that information into your question, not a comment. That way it can be used for al answers.. A 10 Hz clock is most definitive to slow for a Z80 SIO. Check the datasheet, it does have certain maximum clock duration, thus minimum frequency. IIRC it's something like 1.5 MHz IIRC. Any clock lower than that will be off spec.
    – Raffzahn
    Apr 22, 2021 at 20:47
  • what am I missing here ? On SIO datasheet, for TcC (Clock Cycle Time), it gives a minimum but the maximum is DC. I read this as, "clock cycle can take forever".
    – Charles
    Apr 23, 2021 at 10:51
  • @Charles Yeah, bit SIO has not only a minimum clock speed, but as well a relation between system an transmission clock of the first being at least 5 times the later. So clocking the sytem at 10 Hz while feeding the SIO 1.8 MHz seems a bit screwed.
    – Raffzahn
    Apr 23, 2021 at 12:31

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