The left side of this schematic is correct, but we have to find errors in the right side. I know that the pins 1 and 3 in mempin should be connected to busrq and busack. I am unsure about the buffers: BUFADDR1, BUFFADDR2 and BUFDATA. Shouldn't they be TTL version (for example 74LS541 instead of 74HC541N), cause the outputs of the z80 are in TTL standard. Are there any other problems with this central unit?
I see some issues, but since this is an assignment, I shouldn't provide a complete solid answer right away. However:
- There are many Z80 variants out there. You may want to know exactly which chip is being used. Personally, I would tend towards using HCT-series logic there if you need TTL compatibility. However, I believe the I/O may be CMOS.
- Look at the conditions under which the bus transceivers are enabled (all three). Do they make sense?
- Does it make sense to use the post-buffer signals to drive the enable inputs on the bus transceivers? That adds an extra delay to enabling those. Doesn't that mean that the address signals will start being driven after the MREQ signal has propagated out to devices? That being said, the opposite problem could present itself if the direction of the data buffer (WR) wasn't post-buffer. May want to consider the enable to the data buffer being derived from RD, WR, and (if applicable) BUSAK.