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Reading over some old articles on Alpha I realized I really didn't understand PALcode. So I did a little reading on that.

PALcode is stored in main memory, is written in Alpha ML, and is called by a table entry. On calling a PAL instruction, it spills the pipeline, looks up that entry number from PAL_BASE, and JSRs to that address.

So isn't that basically identical to what any other platform would call a vectored interrupt?

Is there something else? Special instructions or internal data that is only accessible via PAL?

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    Yes, I think that there are special capabilities accessible only to PAL code. – Erik Eidt May 3 at 16:23
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PALcode is not just the 'extra instructions' - it also provides other support for the hardware. The architecture manual mentions interrupt dispatching, power-up initialization, and so on.

The manual goes on to say (1992 version, chapter 6):

PALcode is written in standard machine code with some implementation-specific extensions to provide access to low-level hardware. This lets an Alpha implementation make various design trade-offs based on the hardware technology being used to implement the machine.

As well as access to such mechanisms, PALcode runs with interrupts off, and I-stream MMU traps are disabled - this latter is apparently necessary so PALcode can assist in memory management.

In short, it's running in a special mode, and it can be as special as the hardware designers want it to be. PALcode is machine-specific but is intended to be used to present a consistent interface to the OS.

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  • From your description, it sounds like PALcode is the Alpha equivalent to x86 System Management Mode. (i.e. A processor mode used to implement machine-specific things invisible to the OS, such as APM or PS/2 keyboard/mouse emulation on a USB-based system.) – ssokolow May 3 at 22:58
  • Maybe, though I know little about SMM. But PALcode seems to have many lower-level concerns, such as dispatching interrupts, that I suppose to be handled by microcode on x86. I found this manual on writing PALcode, which may be of interest. – another-dave May 3 at 23:37
  • This still sounds like vectored interrupts - they also run in priv mode with interrupts off, have access to hardware (they're for drivers after all), etc. The MMU part seems unique, but earlier industrial machines generally lacked these. – Maury Markowitz May 4 at 12:26
  • The 'access to hardware' includes access to mechanisms that kernel mode does not have access to - that makes this a little different. Also, PALcode seems to be what implements vectored interrupts for devices. – another-dave May 4 at 14:22
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On the Alpha, PALcode acts as a replacement for microcode (§1.1). Low-level functions that would normally be controlled by microcode are instead handled using code stored in main memory (§2.1). This consists of regular Alpha machine code augmented with five additional opcodes that provide access to normally inaccessible internal registers (§1.3). Calls to PALcode are basically a form of interrupt; when the processor needs to access a PALcode function it does so through a jump table stored in main memory (§2.1). From that section:

PALcode can be invoked by the following hardware and software events:
• Reset
• System hardware exceptions (machine check, arithmetic trap)
• Interrupts
• Memory-management exceptions
CALL_PAL instructions

Note that, e.g., after handling hardware-specific tasks a PALcode interrupt handler may then pass control to an OS-provided handler or userland code (Table 2-1).

Full details can be found in PALcode for Alpha Microprocessors System Design Guide (thanks to @another-dave for that link). All references above are to that document.

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  • Section 4.7 of PALcode for Alpha Microprocessors - System Design Guide describes how interrupt dispatching needs to be implemented in PALcode. – HABO May 6 at 0:56

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