Where does the 6502 store the low order byte after fetching for read instructions?

Question

I am trying to get a mental model of how the 6502 operates. I am going off this image: However please suggest a better one if it helps understanding .

On this website it describes how a read instruction occurs.

    Read instructions (LDA, LDX, LDY, EOR, AND, ORA, ADC, SBC, CMP, BIT,
                        LAX, NOP)

        #  address R/W description
       --- ------- --- ------------------------------------------
        1    PC     R  fetch opcode, increment PC
        2    PC     R  fetch low byte of address, increment PC
        3    PC     R  fetch high byte of address, increment PC
        4  address  R  read from effective address

My question is where do we store the low order byte after step 2 above? The obvious choice is the ABL however, would step 3 not overwrite this fetching the high byte of the address?

Answer 1

Have a look at this blockdiagram, it matches the real layout of the 6502 a lot better. Also, have a look at visual6502.org, you'll find more details about the chip to the tiniest detail, including a working simulator.

To definitely answer your question, you can just run the instructions in the simulator, and I'd have to do it myself, but I'd suspect the adder hold register (ADD) would hold the low byte address, as it can be directly output to ABL using the ADL bus.