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I am trying to get a mental model of how the 6502 operates. I am going off this image: this image However please suggest a better one if it helps understanding .

On this website it describes how a read instruction occurs.

    Read instructions (LDA, LDX, LDY, EOR, AND, ORA, ADC, SBC, CMP, BIT,
                        LAX, NOP)

        #  address R/W description
       --- ------- --- ------------------------------------------
        1    PC     R  fetch opcode, increment PC
        2    PC     R  fetch low byte of address, increment PC
        3    PC     R  fetch high byte of address, increment PC
        4  address  R  read from effective address

My question is where do we store the low order byte after step 2 above? The obvious choice is the ABL however, would step 3 not overwrite this fetching the high byte of the address?

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Have a look at this blockdiagram, it matches the real layout of the 6502 a lot better. Also, have a look at visual6502.org, you'll find more details about the chip to the tiniest detail, including a working simulator.

To definitely answer your question, you can just run the instructions in the simulator, and I'd have to do it myself, but I'd suspect the adder hold register (ADD) would hold the low byte address, as it can be directly output to ABL using the ADL bus.

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    Looking at Hansons diagram (Always use the new version) and Visual 6502 is always a good idea. Except, Visual6502 makes it a bit hard see this exact mechanic, as DL and A/B registers aren't shown, and expanded trace only shows ALU output (where it shows up). It's a tiny dance. During T2 the low byte gets stored in DL. In T3 it moves via ADL to ALU B-Input, zero gets added and put into ALU out (ADD) and outputted to ADL(again), where ABL picks it up during the next cycle. Nice little dance reusing existing real estate.
    – Raffzahn
    May 4 at 22:33
  • @Raffzahn that's what I would have expected, and it also sets the stage for the $abs,X and $abs,Y addressing modes, where you'd have to use the ALU anyway.
    – dirkt
    May 5 at 4:44

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