I am stuck by designing a 8 Slot 16 Bit ISA Backplane

Do I have to terminate an ISA bus?

My search results are:

  • No termination at all

  • Some homebrew projects use active termination for all signals

  • The Intel ISA Bus Specification describes pull-up and series resistors on selected signals (Address/Data Bus are untouched)

Intel ISA Spec

What's the right solution? I am a bit confused.

Thank you in advance :-)

  • 3
    I think to get the larger picture I have to ask what do you mean by termination? Simply having pull-up resistors of 300 to 4700 ohms on TTL outputs or inputs does not count as electrical termination yet. Electrical termination is a term for preventing reflections from the end of the bus, and for that the usual way would be to have maybe 220 ohms to ground and 330 ohms to 5V, and that would be a huge load for a TTL chip to drive.
    – Justme
    May 19 at 4:59
  • Yes, i realy mean Termination. ;-) Sorry the delay, I searched through Servicemanuals I could find from Classic Computer based on ISA-Bus. Most of them have a simple RC-element against Signal Ground. Funny fact: By searching for pictures of the PCBs you can see that on some PCBs the filters are not populated. Maybe I'm just driving myself crazy here for the slow ISA bus? In any case, I will also provide RC filters in the layout.
    – Gonzo
    May 22 at 21:08

The classic ISA bus has very little need for bus termination. For example the first IBM PCs, such as the PC, XT and AT for example did not use any bus termination, and their ISA bus worked fine.

So, in short the answer is, no you don't have to terminate the bus, as depending on how you do it, it might just make things worse. The cards on the bus are definitely not designed to sit in a system that has DC or AC terminations, so for example they might have trouble driving a terminated data bus, due to more DC current it takes to drive it, or due to the increased capacitance of AC termination.

The reason why it can work without termination is strictly the speed it operates. Not the clock speed that can be measured in MHz, but the speed of the logic signal edges. The used logic chips of the computers mentioned above are LS TTL or ALS TTL types, which on a properly designed backplane PCB will not cause too much trouble. Some overshoot and undershoot may be present and that is fine as long as it does not cause ringing.

The "some homebrew projects use active termination" is what they chose to do. One of the projects seem to work better with it, but it did mix faster F series TTL chips with ALS TTL chips, so faster chips mean it is harder to make it more reliable, and the PCB was only two-sided, instead of having four layers to include reference planes for the signals, so crosstalk can be an issue. So, a good desing might require termination to work, a better design doesn't require termination to work.


Pull-ups are required (for the lines that are used) but the series resistors are optional. You may wish to place 0Ω links (on /IORC et al.) between the processor's bus and the ISA bus; if you encounter problems these could be replaced with series resistors (e.g. 22Ω, as suggested by Intel). A more common technique1 for bus termination is to use a resisitve divider (pull-up + pull-down) on each signal; these could be left unpopulated if not needed. The same could be done for the pull-ups; unneeded pull-ups could simply not be populated.

For reference, here's an ISA-based 8088 SBC (schematic) and its backplane (schematic). There is no bus termination (via series resistors or otherwise) but pull-ups are present on the CPU board:

Pull-ups resistors

Note that the pull-up values on this SBC are a bit weaker (higher values: 10kΩ) than what the Intel appnote suggests (4.7kΩ). Other ISA bus pins are simply not connected (the ones that Intel lists stronger pull-ups for). It has been noted that termination may be needed for stable operation (see first link below).

1 Bus termination is a somewhat complex topic. For a detailed discussion of it in the context of the SBC mentioned above see this page. For another take on the topic see appendices A and B of this document.

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