but I can't find any explicit documentation.
The documentation for the Z80 behaviour is in its manual. For the way the CPC hardware handles it, you may need to see these circuits. It may, for example hold an IRQ until it is accepted.
but what happens in the case of the prefix? Is the interrupt acknowledged after the next instruction has been executed?
The same way as when an interrupt occurs half way through an instruction.
The reason why I'm confused about this is that I read that the interrupt request signal generated by the Gate Array only lasts about 1.4 microseconds, which even is shorter than some instructions.
The linked page does not really show if that is linked to any kind of CPU response or not. It would be unusual to assert INT only for a time that short. To me this rather seems like a single shot recorded where the CPU simply reacted to the Interrupt within 1.4 µs. Without further clarification, I'd be a bit sceptical about this being valid in general.
Then again, the CPC timing is kind of complicated. For one thing, instructions are synchronized to video execution, and timer handling does include a correction factor, so the answer to this case may be less Z80-related and more due to the way the CPC operates.
Z80 Interrupt Initiation
The Z80 Technical Manual does describe the interrupt signals and their behaviour already in full on page 8:
(Taken from Z80-CPU Technical Manual of 1976)
As described, the IRQ is level sensitive, so any request must be held low until it is recognized - any circuit design should hold it low at least until acknowledged (IORQ active while M1 is active), or better until service started. It will only be recognized at the beginning (raising clock) of the last T-State of the last instruction and only if there is no higher priority issue - such as NMI or BUSRQ. To do so it must be low for at least 80 ns before the rising clock edge.
NMI in contrast is edge triggered. An occurrence at any time during processing will be recorded (minimum needed pulse width is 80 ns), but handling is postponed until the end of the actual instruction (*1).
For more information, there is a high quality 'rewrite' of the May 1978 The Z80 Family Program Interrupt Structure.
*1 - In fact, the detailed description of NMI on page 17/18 seems to hold a copy/paste error - that got corrected in later manuals.