Reading over the design of the TMS9900 it is often claimed that the R0 - R15 registers are in RAM because semiconductor RAM ran at the same speed as the CPU and therefore there was no penalty to doing so
But unless I'm missing something, this statement seems wrong.
I do not see any specialized access lines to memory for the registers, so I assume a normal memory read is required.
Jup, so it is, (usually) every other cycle is a memory cycle.
That would normally be >0 cycles and have to be latched internally, no?
Is there something I'm missing here? Cycle stealing perhaps?
No, except that cycle and speed is kind of an arbitrary concept, used different in each designer/team. This starts by what one does call a cycle, and how internal cycles are seen from the outside. Just take the 8080 and its concept of machine and clock cycles.
Or our beloved 6502. A 1 MHz 6502 runs at 1 MHz, right? No, it runs at 2 MHz! It does two internal cycles per external clock. It's always an internal cycle (ALU cycle) followed by a memory cycle (*1)
The 9900 works quite similar, here as well each other machine cycle is a memory cycle. Except that each of these machine cycles last two clock cycles. Let's look at a typical instruction, adding two register:
(this will be rather simplified for in detail description you may want to consult the manual)
- Memory: Read instruction
- Internal: Decode Instruction
- Memory: Read R1
- Internal: Setup addition
- Memory: Read R2
- Internal: Add
- Memory: Write R1
So this addition takes 7 machine or 14 clock cycles. It does sound like an awful wast of cycles, right?
So, how does a 6502 do it?
- For a fair comparison we look at each half clock cycle separate.
- In addition we use a ZP instruction to make it a fair one.
- We ignore as well istruction differences and simply assume a 6502 ADC is the same as a 9900 A. But most of all
- We ignore the 16 bit nature of the 9900, after all, there could have been a 6516 with 16 bit data bus as well (*2)
- 1.1 Internal: Housekeeping for the last instruction
- 1.2 Memory: Fetch OP
- 2.1 Internal: Increment PC, Decode OP
- 2.2 Memory: Fetch ZP-address
- 3.1 Internal: Increment PC
- 3.2 Memory: Fetch data from ZP
- 4.1 Internal: Add and settle result in A
Since the first half cycle belongs to the previous instruction, we come down to 6 steps taken (albeit not having written back to memory at all) and only 3 'real' cycles, isn't that great? And quite fast?
Now, serious, cycles are Hokus Pokus, terms design magicians pull out of their hats to impress the audience. When looking behind that facade, all that really exists are are memory cycles - which as well is the start of the argument: memory speed
So let's assume we use 500 ns RAM (*3) with the above CPUs_
- Doing the 6 machine cycles of a 6502 will take 3 µs, while only half the bandwidth of the memory is used.
- Doing the 7 machine cycles of a 9900 will take 3.5 µs, using a bit less than half of that for memory access.
It's exactly the pipelining half cycle the 6502 is faster for such simple cases. Except, the 9900 has already used that time to write back the data to memory as well (*4)
It will get better with more complex instructions, as the 9900 can have several internal cycles in sequence, whereas the 6502 always has to do a memory cycle as well (*4) - nicely shown with page crossing indexing.
Long story short:
Never look at fancy clock rates, but focus on memory timing when comparing CPUs
But, but ...
... couldn't the CPU have been much faster with registers on chip?
Yes, it could, but what for? It would have cost a lot of real estate - 16 registers with 16 bits are 256 bits. With addressing logic this cones down anywhere between 1000 and 2000 transistors - quite some dough back then. Why invest that? Sure, taking above scheme, it may have speed up the execution from 14 to maybe 8 clocks, while doubling the price? (*5)
Not to mention that putting them on chi will introduce all the overhead of register saving - something eating up many instructions and memory cycles with other machines.
And finally there is the historic part - the 9900 is the single chip implementation of the way older 990, designed at at time when memory was not only expensive, but transistors even more rare.
*1 - And when looking really close we even see 4 cycles, as each edge of each phase is used to trigger certain workings.
*2 - No I will not go down that hole of describing all the pitfalls of such a CPU.
*3 - For this we ignore all the fine print about memory selection and simply say we have a memory that delivers a word within 500 ns.
*4 - The burden the simplified memory interface brings.
*5 - Price increase isn't linear. It's safe to assume that a 9900 was already close to what could be made economic in 1976. Increasing that by 15-25% would have for sure resulted in a way higher cost than those percentage.