The standard Sinclair ZX Spectrum only used mode 1 and mode 2 interrupts but the Z80 also has a mode 0 interrupt that the original Speccy never used.

But there were many exotic clones of the ZX Spectrum. Did any of those use interrupt mode zero?

  • 4
    Just a comment, because it is difficult to prove the negative - I doubt it, since mode 0 needs some circuitry to force an instruction to the CPU BUS, and if you want to use the original ROM, the only reasonable instruction to use is RST7, and that is exactly the same as mode 1 (and no additional components needed). If you want fine grained interrupts, and you can use a non-compatible ROM, then mode 2 is more useful (you can define jump table). Remember that mode 0 was there only because of backward compatibility. Commented Jun 14, 2021 at 5:56
  • @RadovanGarabík: I thought not all of the clones used the original ROMs. I think the Brazil one's didn't. Commented Jun 14, 2021 at 6:38
  • I guess almost all the clones made some tweaks, but mostly kept the ROM compatible (in particular, RST0 to RST7 locations are used for well defined purposes and modifying them to serve mode 0 interrupt could made your machine quite incompatible for a lot of programs). TIMEX 2068 was an exception in this regard. Commented Jun 14, 2021 at 6:45
  • Proof of non-existance is impossible, but it's very, very unlikely. (not a Z80 machine that uses mode zero, but rather a Spectrum clone that uses that IM). That box wouldn't have been close to a ZX Spectrum. I think even finding any genuine Z80 machine that uses IM0 should be difficult.
    – tofro
    Commented Jun 14, 2021 at 10:38

2 Answers 2


IM 0 is the backwards-compatibility mode with the i8080 CPU. You have to use some external circuit to provide desired RST 0..38h instruction. RST 0 is effectively the same as RESET, RST 38h is the same as IM 1 mode provides.

All the other RST addresses have their own meaning in the ZX Spectrum ROM (see):

  • RST 00h is RESET
  • RST 08h is ERROR
  • RST 10h is PRINT A CHAR
  • RST 18h is parsing helper COLLECT A CHAR
  • RST 20h is also parsing helper COLLECT NEXT CHAR
  • RST 30h is MAKE A SPACE
  • RST 38h is THE INTERRUPT (IM1)

The main benefit of using the RST instructions for often-called subroutines is to shorten your code. A CALL instruction uses 3 bytes but a RST only 1.

So here is the deal:

  1. You can make a compatible machine with a compatible ROM, but you can not meaningfully use any other RST than 38h (or 00h for RESET).


  1. You can make a less-compatible machine with RST handling and IM 0, but you can not use the original ROM. If you want to use the IM 0 mode, you have to relocate all those routines, call them via long CALL (instead of short RST), and break compatibility with a lot of software, so you cannot call it "a clone" anymore.
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    There's a similar, but different (IIRC) set of RST addresses when the ZX Interface 1 ROM is swapped in, too. Commented Jun 15, 2021 at 13:46
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    @TobySpeight, the RST addresses are the same - they're fixed by the Z80 instructions. It's the functions of the RST subroutines that are different.
    – TonyM
    Commented Jun 15, 2021 at 14:55
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    Yes @TonyM, I didn't phrase that very clearly. I obviously meant different functions at those addresses. Commented Jun 15, 2021 at 14:57
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    @TobySpeight There is no space for details, but briefly: ZXIF1 does a hack with RST 08h: when CPU reads an instruction from 0008h, the ZXIF1 glue logic mapped on its own internal ROM, so this is the way the ZXIF1 takes control. RST 08h is the ERROR routine, so when the ZX ROM find something like LOAD *"m";1;"xyz", throws a syntax error - and this is the moment ZXIF1 ROM takes its time and does its own syntax check, or perform a desired operation. Commented Jun 15, 2021 at 15:30
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    @Martin, what I meant was that the IF1 ROM also contains frequently-used routines at 10, 18, 20, 28, 30 and 38. (I think the 38h function is pretty much a copy of the main ROM, as this is the IM1 interrupt target). Commented Jun 15, 2021 at 15:57

Actually, original 48k Speccies also work in IM0 mode. During the vector read (/IORQ+/M1) the CPU reads all 0xFFs from the bus (because of the pullups), thus reading RST #38 instruction. In other words, IM0 mode on the original speccies works identical to IM1 mode.

For anything more meaningful in IM0 mode on Speccies, one would need to use intel's 8259 interrupt controller that is capable of generating full call ADDR instructions for the CPU to fetch in IM0 mode. which is identical to what 8080 does during its interrupt entry.

Another option is to have ROM swapped off (which is possible on Speccies). If one put there RAM with proper code at every RST point, IM0 could be used as a cheap substitute for IM2, with only 3 bits of interrupt vector (out of 7 for IM2).

  • 1
    That's only guaranteed on unexpanded 48k Speccies though, right? Which sounds like a stupid question, but one reason people advise a 257-byte lookup table for reliable use of IM 2 is that some implementations of the Kempston joystick interface put data on the bus during an interrupt acknowledgement. Or, at least, someone once said that at least one of them did, and that idea has taken root. I've no idea of whether that's apocryphal.
    – Tommy
    Commented Jun 15, 2021 at 14:58
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    Yeah, and also some ZX Spectrum clones are known to require 257-bytes IM2 table. Anyway it might be thought as a design flaw of those clones or expansion devices.
    – lvd
    Commented Jun 15, 2021 at 17:33

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