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Early microprocessors often used NMOS or PMOS transistor technology (see this question for their use in early Intel chips). Techniques such as implementing registers with dynamic memory cells (instead of static logic) and precharging the buses were often used to save on the transistor counts. However, such techniques meant that the processor could not tolerate a stopped clock signal, as charge would eventually drain away.

In contrast, CMOS processors are more likely tolerate a stopped clock. The RCA 1802 is a good example; the clock may be stopped indefinitely. The PowerPC 750 was CMOS and dynamic, but its radiation-hardened version RAD750 is CMOS and static.

Were there any NMOS/PMOS processors that would still function properly after the clock was stopped and restarted?

Related:

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  • precharge isn't mainly used to save transistors, it's used to increase the slew rate on transition in one direction. Rather than pulling the bus from an arbitrary state, it's preloaded the state which it's slow to get into ("high") so that it only needs transitions in the "fast" direction (ie to "low") during active phases. Precharge does slowly decay, just like a cap. Wait long enough and all the charge has gone. In reality lots of things piggy back on precharge ("need FF?, no problem, here's an idle bus") or omit passive pull up, so you can't just not do it and rely on resistive loading. Dec 3 '21 at 18:40
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As mentioned, being able to operate static isn't tied to production process, but the logic design. Thus there were of course static CPUs. A good example might be the Valvo-Signetics 2650 one of the more successful of the lesser known ones. Another example might be Texas' 9900, but I'm not entirely sure without checking its data sheet.

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  • Is the Valvo version different than the original? Jun 21 '21 at 21:12
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    @MauryMarkowitz Erm, I somehow don't understand your question. Using Valvo, Signetics or Philips was a marketing thing defined due region and time.
    – Raffzahn
    Jun 21 '21 at 21:32
  • Indeed, which is why I asked - was there a reason to say "Valvo-Signetics" as opposed to simply "Signetics"? Jun 21 '21 at 22:47
  • Nice find. Wikipedia link added for the 2650; the WP article confirms NMOS, and an advertisement confirms that it is static. The 9900 is also NMOS, but the data sheet is unclear on clock rates. Table 4.4 lists timing requirements, but only "typical"; the minimum and maximum columns are entirely blank.
    – DrSheldon
    Jun 22 '21 at 3:42
  • @MauryMarkowitz Simply for understanding. As the names have been used different in different regions, not everyone will relate to either alone - at some point I simply started to use it that way - not to mention that it has been used by them hyphenated as well :))
    – Raffzahn
    Jun 22 '21 at 11:28
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Early NMOS Z80 CPUs were "half"-static -- they tolerated indefinite holding of the clock in '1' state, but not in '0'.

Z80 tech manual, pg.75

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  • I wonder if there were any devices whose internal logic was "half-static", but which included self-timing circuits to control how long internal circuitry was in a "float" state? A hypothetical example might be a CPU that internally uses a non-overlapping two-phase clock, and limits how long both phases may be idle, but which like the 6502 generates the two-phase clock from an externally-applied one-phase clock.
    – supercat
    Dec 1 '21 at 20:58
  • @supercat I can't see how starting doing internal-clocked things when external clock halts can be combined with the fact that external clock could start toggling at any moment unpredictably. BTW, Z80 was half-static in a sense that NO dynamic latches would be left in a 'remembering' state during clock='1'.
    – lvd
    Dec 2 '21 at 12:06
  • The external clock would not be allowed to "start toggling unpredictably", but after each change of state would be required to remain stable for a specified minimum time, and all self-timed events within that chip would occur within that time.
    – supercat
    Dec 2 '21 at 15:50
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I was envisioning such a construct as being useful in something like a shift register, which would have back-to-back pairs of inverters that would normally be cross-connected via pass gates, but advancing the shift state would float the cross-connecting gates in every pair, momentarily connect first inverter of each pair to the second inverter of the previous pair, and then start connecting the second inverter in each pair to the first before reconnecting the first back to the second. This would add the ability to have the shift register hold its state indefinitely at a cost of only one extra pass gate per bit and an extra clock phase wire.

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