It appears that at least some pre-IEEE 754 computers had only one hardwired floating point rounding mode, e.g. away from zero as in PDP-11 (page 154 of PDF).

Which historical architectures were the earliest ones to cater to the need for the ability to switch floating point rounding modes in software? Not necessarily at the same level of detail as IEEE 754, just two different modes switched by flipping a bit in a status register or using different opcodes would be enough.

A data point: M-20, designed in 1955-1958, had different arithmetic instructions for operations with or without normalization or rounding.

  • The CDC 6600 (from 1964) had different instructions to e.g. add without rounding and normalization, with rounding, and with a double length result. So other ways of rounding could be implemented easily, but there was no status bit. Does that count?
    – dirkt
    Jan 6, 2017 at 11:26
  • And as for "status bits that influence arithmetic", the Burroughs 5000 (from 1961) had char and word oriented execution modes; in the first, arithmetic is BCD, in the last, floating point (with one type of rounding). Does that count? :-)
    – dirkt
    Jan 6, 2017 at 11:28
  • 2
    Also, "what was the first architecture do to X" is a bit difficult to answer unless someone knows all the early architecture intimitely in all details (unlikely). "What were early architectures to do X" might allow actual answers.
    – dirkt
    Jan 6, 2017 at 12:02
  • @dirkt: Yes, CDC will count (a status bit vs. an opcode bit doesn't make a big difference); was Burroughs BCD representation floating or fixed point?
    – Leo B.
    Jan 6, 2017 at 16:55
  • 1
    Right; I'm interested specifically in the computational math aspect. Some kind of balanced rounding is needed for regular computations to avoid loss of precision, and suppressed rounding is needed for an efficient implementation of multi-precision floating point.
    – Leo B.
    Jan 6, 2017 at 18:02

1 Answer 1


The IBM System/360 had separate instructions for (Add, Subtract, Multiply, Divide) Normalized and (Add, Subtract, Multiply, Divide) Unnormalised. That feature remained in /370, /390, and zSeries. (zSeries now does IEEE arithmetic as well.) The earlier STRETCH (IBM 7030) machine also offered this choice. In fact, the 7030 had three choices: unnormalized, normalized (shift 0s in when normalizing), and "Noisy" (shift 1s in when normalising). My e-copy of the Stretch reference manual is dataed 1960 and the first machine was shipped in 1961, according to Wikipedia.

Interval arithmetic, relying on the towards -infinity and towards +infinity rounding modes, was understand and used in the 1960s, but I don't know when hardware support for those modes was introduced. Certainly the B6700, DEC-10, and S/360 didn't have them. Computer architects had a tendency to focus on the speed of floating-point arithmetic as their top priority.

  • I thought about that IBM STRETCH could be a good data point when first posting but then I've found an earlier example. It is now my understanding that Sergey A. Lebedev's (en.wikipedia.org/wiki/Sergey_Lebedev_%28scientist%29) ideas about the floating point with selectable rounding modes could have been implemented starting from the early 1950s in his BESM-1.
    – Leo B.
    Jan 9, 2017 at 19:36

You must log in to answer this question.

Not the answer you're looking for? Browse other questions tagged .