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It appears that at least some pre-IEEE 754 computers had only one hardwired floating point rounding mode, e.g. away from zero as in PDP-11 (page 154 of PDF).

Which historical architectures were the earliest ones to cater to the need for the ability to switch floating point rounding modes in software? Not necessarily at the same level of detail as IEEE 754, just two different modes switched by flipping a bit in a status register or using different opcodes would be enough.

A data point: M-20, designed in 1955-1958, had different arithmetic instructions for operations with or without normalization or rounding.

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  • The CDC 6600 (from 1964) had different instructions to e.g. add without rounding and normalization, with rounding, and with a double length result. So other ways of rounding could be implemented easily, but there was no status bit. Does that count?
    – dirkt
    Jan 6, 2017 at 11:26
  • And as for "status bits that influence arithmetic", the Burroughs 5000 (from 1961) had char and word oriented execution modes; in the first, arithmetic is BCD, in the last, floating point (with one type of rounding). Does that count? :-)
    – dirkt
    Jan 6, 2017 at 11:28
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    Also, "what was the first architecture do to X" is a bit difficult to answer unless someone knows all the early architecture intimitely in all details (unlikely). "What were early architectures to do X" might allow actual answers.
    – dirkt
    Jan 6, 2017 at 12:02
  • @dirkt: Yes, CDC will count (a status bit vs. an opcode bit doesn't make a big difference); was Burroughs BCD representation floating or fixed point?
    – Leo B.
    Jan 6, 2017 at 16:55
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    Right; I'm interested specifically in the computational math aspect. Some kind of balanced rounding is needed for regular computations to avoid loss of precision, and suppressed rounding is needed for an efficient implementation of multi-precision floating point.
    – Leo B.
    Jan 6, 2017 at 18:02

2 Answers 2

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The IBM System/360 had separate instructions for (Add, Subtract, Multiply, Divide) Normalized and (Add, Subtract, Multiply, Divide) Unnormalised. That feature remained in /370, /390, and zSeries. (zSeries now does IEEE arithmetic as well.) The earlier STRETCH (IBM 7030) machine also offered this choice. In fact, the 7030 had three choices: unnormalized, normalized (shift 0s in when normalizing), and "Noisy" (shift 1s in when normalising). My e-copy of the Stretch reference manual is dataed 1960 and the first machine was shipped in 1961, according to Wikipedia.

Interval arithmetic, relying on the towards -infinity and towards +infinity rounding modes, was understand and used in the 1960s, but I don't know when hardware support for those modes was introduced. Certainly the B6700, DEC-10, and S/360 didn't have them. Computer architects had a tendency to focus on the speed of floating-point arithmetic as their top priority.

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  • I thought about that IBM STRETCH could be a good data point when first posting but then I've found an earlier example. It is now my understanding that Sergey A. Lebedev's (en.wikipedia.org/wiki/Sergey_Lebedev_%28scientist%29) ideas about the floating point with selectable rounding modes could have been implemented starting from the early 1950s in his BESM-1.
    – Leo B.
    Jan 9, 2017 at 19:36
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In 1959 George Forsythe proposed a stochastic rounding mode in Forsythe, George E. “Reprint of a Note on Rouding-off Errors.” SIAM Review, vol. 1, no. 1, 1959, pp. 66–67.

Noting that "...in the integration of smooth functions the ordinary rounding-off errors will frequently not be distributed like independent random variables" (he mentions specifically the empirical finding that ENIAC rounding errors had strong biases) he proposed "a random rounding-off procedure which make ε a true random variable" (p. 66, emphasis his).

The procedure, "where u is "rounded up" to ⌈u⌉ + 1 with probability v, and "rounded down" to ⌊u⌋ with probability 1 - v, the choice being made by some independent chance mechanism" is essentially identical to what we now call stochastic rounding.

The paper contains a footnote that the note was originally circulated at the National Bureau of Standards (Now NIST) in 1950, so rounding modes like this one could have been circulating for the whole decade.

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    Has this ever been implemented? The uncertainty it would add to software regression testing is a huge red flag. Apr 24 at 16:02
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    Stochastic rounding is widely used and has valuable features for both statistics and machine learning. Remember that random need not mean non-deterministic. If you use a pseudorandom generator and set a seed you can recover each rounding decision between runs. Apr 24 at 16:33
  • @AdamHyland Adding a 64-bit or even a 128-bit LFSR, whose state would be saved/restored at context switching, to a HW implementation of an IEEE 754-compliant FPU requires a trivial number of extra gates. I wonder if such an implementation exists.
    – Leo B.
    Apr 24 at 23:10
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    royalsocietypublishing.org/doi/10.1098/rsos.211631 is an open access survey of stochastic rounding implementations with lots of information about this. Apr 24 at 23:54
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    @LeoB. There is also this recent paper with a proposed implementation similar to what you describe: arxiv.org/abs/2001.01501 Apr 24 at 23:56

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