Looking at a schematic of the Juppi I think you can safely assume that a floating data bus is read as 0xFF.
There are several memory chips connected but none of them is active because /MREQ is not active during the interrupt acknowledge cycle.
And then there are the video RAM and the character RAM. In order to separate their data bus from the other memories, serial resistors are inserted. This way the video output can be maintained while the CPU accesses the other memories.
The data bus of the character RAM is directly connected to the pixel shift register. And here is the part that kind of pulls up the level. This shift register is a TTL chip 74LS166. The "LS" series has inputs that read "high" when left floated, see the Wikipedia page on "Transistor–transistor logic".
So each data bus pin of the CPU has a path to VCC, first the separating resistor of the Juppi of 1kOhm, then the emitter diode of the input transistor inside the 74LS166, and finally the base resistor of nominally 4kOhm inside the 74LS166.
This question circled in the back of my brain, and this answer is not complete. Unfortunately I don't have a real Ace to check, but this is what showed up.
- If the video RAM is enabled to provide a character to the character RAM at the time the CPU expects the vector, the character will be read as such.
- If the character RAM is enabled to provide a pattern to the shift register at the time the CPU expects the vector, the pattern will be read as such.
Hm... this might explain why 0x20 is read most of the time. It is the code for
space. (Possible experiment: Fill the screen with any other character and see which value is read.)
Conclusion: There is no definite value. You cannot use IM2 reliably.