(I'm assuming a memory cycle of 500 ns, without wait states.)

According to the 68000 bus diagram, there are 4 CPU cycles for a memory cycle, so an external frequency of 8 MHz. However, things are happening on the falling edges of the clock, so it seems like some internal state machine is running at 16 MHz.

68000 bus diagram

According to the 65816 bus diagram, there is only one CPU cycle for a memory cycle, so for a 500 ns memory cycle, an external CPU frequency of 2 MHz.

65816 bus diagram

Let's take a basic accumulator increment instruction (INC A / ADDQ #1, D0).

According to their documentation, each of those processors is able to prefetch instructions. The 65816 block diagram shows a dual bus for feeding the ALU operands. I assume that it's the same for the 68000 (couldn't find a block diagram, though).

I expect thus that the instruction would be internally executed like this:

1.  ALU_A <= A/D0; ALU_B <= #1; ALU_OP <= ADD
2.  A/D0 <= ALU_RES

The instruction takes only one bus cycle on the 68000, but two bus cycles on the 65816. I would expect that it could use a pair of internal states to fit that instruction in a bus cycle. But perhaps those internal states can't be used except for generating bus signals?

Let's consider a more complex instruction on the 68000:

ADDQ.L #val, D0

Now, as the 68000's ALU is 16 bits wide, I anticipate the following sequence (I make the reasonable assumption that there's an immediate sign extension circuit feeding one ALU operand, B in my example):

1.  ALU_A <= D0.L, ALU_B <= S_EXT(val).L, ALU_OP <= ADD
2.  D0.L <= ALU_RES
3.  ALU_A <= D0.H, ALU_B <= S_EXT(val).H, ALU_OP <= ADDX
4.  D0.H <= ALU_RES

If using S0-S7 states, there's more than enough states to run that sequence. And if for some reason those states can't be used for internal calculations but only for bus signalling, then there's still 4 cycles to the bus cycle. So the instruction should need only 4 cycles. But the documentation tells us that 8 cycles are needed.

The 68000 was build for performance, having a pair of ALU just for address computations. So it looks I'm missing something.

What is the relation between those CPU clocks and internal states?

(I'd prefer to learn to fish than to ask for a fish, but none of the numerous resources I found online about microarchitecture helped me to answer my own question.)

  • 1
    I assume this question is specific to the 68000? I think if the title of the question itself also would include "68000", that would make it easier for anyone who happens to come acress this Q&A in the future.
    – dirkt
    Jul 25, 2021 at 10:23
  • @dirkt: Corrected.
    – airman
    Jul 25, 2021 at 11:07
  • 1
    And BTW, [here](gendev.spritesmind.net/forum/viewtopic.php?t=3023 ) is a link to links to lots of resource of the internal 68000 structure, down to microcode/nanocode level, with results of netlists from decaps, and links to patents. So I'd assume if you go all of through this, you should be able to answer your question (and I'll go through it myself once I can find the time).
    – dirkt
    Jul 25, 2021 at 11:14
  • @dirkt: Very useful resource. Especially this link to "Microarchitecture of VLSI Computers" (mega.nz/#!FQFiUawI!gF5okEJ7vd-1dqhqFbMLgihH5kmLAhfyCLGiJnh5GPY), that includes a chapter on the microarchitecture of the 68000.
    – airman
    Jul 25, 2021 at 11:49
  • 2
    If this is a question about the 68000, then what are the references to the 65816 about? They are two complete different CPU architectures with no relation. The 65816 is a modified 6502, while the 68k is a clean sheet design. Also, the 65 is a heavy optimized design, while the 68k is not 'build for performance' as assumed, but a rather straight school book like design. No nifty shortcuts.
    – Raffzahn
    Jul 25, 2021 at 12:36

2 Answers 2


With the help of the PDF I found in @dirkt's link, I'm able to answer my question.

Yes, there are internal T signal states, each of them running in the active phase of two non overlapping 8 MHz internal clocks.

But no, you can't process data at the rate I anticipated. I forgot about bus precharge (extract from the PDF):

enter image description here

I expect that it's the same for every processor of the era. So that is why I had the same problem understanding the 65816's inner workings too.

  • 1
    Also, from how far I got, it looks like the bus state sequencing and the micro/nanocode execution have a very loose connection.
    – dirkt
    Jul 25, 2021 at 19:53

It is quite typical in chip designs using common IC technology nodes of that era (around 5000 NM NMOS) to require a separate clock phase to precharge any bus signals before they can be used for logic signaling. The NMOS pull-ups (if any!) to a logic high level were mostly too weak or too slow to accomplish this in a single clock cycle without the extra preceding precharge cycle. (Of course, depending on gate widths, cycle time, wire and gate loading capacitance, yada, yada. And lots of spice simulation on hand selected signals, instead of modern timing closure tools.)

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