(I'm assuming a memory cycle of 500 ns, without wait states.)
According to the 68000 bus diagram, there are 4 CPU cycles for a memory cycle, so an external frequency of 8 MHz. However, things are happening on the falling edges of the clock, so it seems like some internal state machine is running at 16 MHz.
According to the 65816 bus diagram, there is only one CPU cycle for a memory cycle, so for a 500 ns memory cycle, an external CPU frequency of 2 MHz.
Let's take a basic accumulator increment instruction (INC A / ADDQ #1, D0).
According to their documentation, each of those processors is able to prefetch instructions. The 65816 block diagram shows a dual bus for feeding the ALU operands. I assume that it's the same for the 68000 (couldn't find a block diagram, though).
I expect thus that the instruction would be internally executed like this:
1. ALU_A <= A/D0; ALU_B <= #1; ALU_OP <= ADD 2. A/D0 <= ALU_RES
The instruction takes only one bus cycle on the 68000, but two bus cycles on the 65816. I would expect that it could use a pair of internal states to fit that instruction in a bus cycle. But perhaps those internal states can't be used except for generating bus signals?
Let's consider a more complex instruction on the 68000:
ADDQ.L #val, D0
Now, as the 68000's ALU is 16 bits wide, I anticipate the following sequence (I make the reasonable assumption that there's an immediate sign extension circuit feeding one ALU operand, B in my example):
1. ALU_A <= D0.L, ALU_B <= S_EXT(val).L, ALU_OP <= ADD 2. D0.L <= ALU_RES 3. ALU_A <= D0.H, ALU_B <= S_EXT(val).H, ALU_OP <= ADDX 4. D0.H <= ALU_RES
If using S0-S7 states, there's more than enough states to run that sequence. And if for some reason those states can't be used for internal calculations but only for bus signalling, then there's still 4 cycles to the bus cycle. So the instruction should need only 4 cycles. But the documentation tells us that 8 cycles are needed.
The 68000 was build for performance, having a pair of ALU just for address computations. So it looks I'm missing something.
What is the relation between those CPU clocks and internal states?
(I'd prefer to learn to fish than to ask for a fish, but none of the numerous resources I found online about microarchitecture helped me to answer my own question.)