I am trying to maintain an old procuct for my employer, based on an HD63B03R which is a 6800-style micro. The crystal on the PCB generates a 4.75MHz clock. I believe from the data sheets found on t'internet for this device thet the CPU internally divides this clock by 4 so in my case the system clock is 1.1875MHz. Documentation says there is a "free running timer" which is used with the Timer Output Compare Register to generate a timer interrupt when the free running timer equals the Timer Output Compare Register - but I can't find anything to say whether the free running timer is incremented by the external clock or the system clock.

The program sets TOCR = free running timer + #FFFF, thus setting the timer interrupt period to the maximum possible. If the free running timer is incrememnted by the system clock then this means the timer will interrupt at intervals approx 55.2ms, or if incremented by the external clock at 13.79 ms intervals. However neither of these figures seem consistent with the program's behaviour.

As a result of these timer interrupts, the program reads an ADC (AD7578) 4 times (each time setting some PORT1 bits to select which analog device is gated to the ADC). So I scoped the (active low) Chip Select for the ADC and saw the expected groups of 4 downward-going pulses with gaps in between. These gaps according to the scope's horizontal scale were 5ms.

I can't relate the 5ms to any of the above figures, there must be something else I don't know. Does anyone else know what that is or where I can find it from?

1 Answer 1


Your analysis seems pretty good. To confirm, the E clock is 1/4 the oscillator frequency. The data sheet also states that the free running counter (FRC) is driven by that same E clock. Your conclusions of the setting of the output compare register (OCR) is also correct.

So how can there be a discrepancy? When I programmed this chip, it was very common to set the initial value to the maximum allowed to give initialization procedures time to conclude. Once running however, the OCR was incremented by a smaller value to increase the rate of interrupts to a higher rate during "normal" operations.

Note here the operation is OCR = OCR + delta and not OCR = FRC + delta, as the former produces interrupts with much less time jitter than the latter.

This incrementing would typically occur in the interrupt service routine and not the main line code. That is where you need to look.

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