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The relevant Wikipedia page has a large gap between 1961 and 1984, not allowing to estimate, even approximately, in what year the symbolic threshold of $1/FLOPS (or, as the wiki table puts it, $1bn/GFLOPS) was crossed.

The threshold of $1/KFLOPS is interesting as well.

In this case the Soviet data points would be mostly useless because the prices of goods not sold outside of the Eastern bloc were in funny money.

If we attempt to accept funny money at a face value, a potential contender – BESM-6 (1967) – still doesn't do it.

A figure of just below $1M was alluded to (in Russian; computed as a multiple of a publicly quoted price of 600K rubles, and the official exchange rate of $1.56 per ruble; I also remember it reported regularly in Soviet newspapers as 0.64-0.66 rubles per dollar), but delivered at most 0.5 MFLOPS using the most generous definition.

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    In the 1960s and 70s many computers did not have floating point arithmetic at all. Even on large mainframes like the IBM S/360, floating point hardware was an optional add-on. That may explain why it's hard to get much comparative data, before processors like the Intel 8086 and 8087 were launched (in 1976 and 1980, respectively).
    – alephzero
    Jan 17, 2017 at 9:55
  • IIRC on the Intel PC CPU side, it wasn't until Pentium that a FPU was guaranteed. From 8086 all the way up to 80486 there were variants in actual use that didn't incorporate a FPU, but where one was available as an extra accessory (assuming your motherboard supported one). 8086/8087, 80186/80187, 80286/80287, 80386SX/80387, 80486SX/80487. For those variants, you had to provide floating-point emulation in software for the case where a physical FPU was not available.
    – user
    Jan 17, 2017 at 15:01
  • @MichaelKjörling The IBM PC only marginally overlaps the relevant time for this question by 3 years, having been released to the market in 1981. The first CPU that could qualify as a floating-point co-processor was apparently the AMD9511 that entered the market as late as 1977.
    – tofro
    Jan 17, 2017 at 15:57
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    I'm not sure I understand the constraints you're putting on the question. Are you restricting the discussion to commercial systems that had floating-point operations in their ISA -- i.e., implemented in hardware or microcode? Are you ruling out any consideration of floating-point libraries running on integer machines? Even on an 8-bit micro, it only takes a few hundred instructions to do a floating-point multiply or add, and there were many ~$1000 systems that could achieve ~1000 FLOPS.
    – Dave Tweed
    Jan 17, 2017 at 17:04
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    @Dave No restrictions. The FLOPS wiki page starts with IBM 1620 which had variable word length (therefore microcoded) and decimal. It is just my guess that the threshold would be crossed by some mainframe around 1970-1972.
    – Leo B.
    Jan 17, 2017 at 17:31

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A Sinclair ZX81 / Timex Sinclair 1000 cost $149 when new, fully assembled, or $99 as a kit, and later $99 (even later $49) fully assembled. It'd easily do a couple hundred floating point operations per second.

Perhaps a VIC-20 might qualify, but I don't think a 1 MHz 6502 would actually do 300 flops (it was introduced in 1980 for $299).

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    In 1969, CDC 7600 was already quite close, $5M for 4 MFLOPS. The expectation is that a mainframe in the early 70s had achieved the milestone; the question is which one.
    – Leo B.
    Aug 1, 2018 at 2:55
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    What's your source for 4MFlops on the 7600? It was a roughly 40MHz pipelined system that could issue 1 instruction per cycle in many situations, with direct hardware floating point support. With a properly optimized program it ought to approach 40MFLOPS. I'd expect 4 from code written in a high level language, but hand optimized code should be much faster.
    – Jules
    Aug 4, 2018 at 16:05
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    @Jules Given that on the 6600 Using the best available compilers, late in the machine's history, FORTRAN programs could expect to maintain about 0.5 MFLOPS and the 7600 generally ran at five times the speed of the CDC 6600, the figure of $1 per realistic FLOPS haven't been reached. I should have linked to that CDC company page 've mentioned in one of my comments above quoting a more precise number of 4 MFLOPS, but I cannot find it now.
    – Leo B.
    Aug 10, 2018 at 0:19
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    @LeoB. - OK, but: (1) the 0.5MFLOPS figure is more about the capability of the compiler, not the machine (the CDC 6600 could manage about 2 MFLOPS on optimized assembly language code) and (2) the five times figure seems very cautious, as it only attributes a 2x speedup above clock rate improvements due to pipelining allowing multiple instructions in parallel, but a well-designed program should be able to exceed that. Again, my suspicion is we're talking about compiler limitations being the issue.
    – Jules
    Aug 10, 2018 at 8:05
  • @Jules For later computers, the FLOPS figure is usually given as measured by a program compiled from FORTRAN or C (Whetstone, Linpack); then, for consistency, the same should be done for retro-computers. Anyway, if the current state of the wiki page for CDC 7600 is to be trusted, it was capable of ~10 MFLOPS on hand-compiled code and sold for around $5 million in base configurations, comfortably crossing the line. But then a somewhat slower but cheaper earlier model of an IBM/360 could have beaten it.
    – Leo B.
    Aug 10, 2018 at 16:16

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