It is not intentionally mirrored, it is just a side effect of making the address decoding hardware for RAM as simple and cheap as possible with a single common 74LS139 chip used for the task, when an 8k area of addresses are reserved for RAM, but only 2k of RAM is present in the 8k area.
If you look at the address map, 0x0000 to 0x1FFF is reserved for the RAM area, that is 8 kilobytes, which means that from the 16-bit memory address, the uppermost 3 bits of the memory address must be zeroes to select RAM area. These three address bits are decoded by the 74LS139 and when all three bits are 0, the RAM chip select is enabled.
This means that the lowermost 13 bits are used within that RAM area to select which RAM address to access. But as there is only a 2 kilobyte RAM present, it only uses lowermost 11 bits of the memory address, and thus the 2 memory address bits from address bus are ignored.
Thus, as long as the CPU wants to access any address in the 8k RAM area, it makes no difference what the two unused address bits are set to, the memory addresses just wrap down to the 2 kilobyte RAM chip.
And that is the reason the CPU sees the single 2k RAM memory chip four times in the 8k window reserved for RAM access.
It would take in fact more complex or just different or additional logic circuitry to try to prevent that from happening, and it would take also additional logic circuitry to be able to expand the memory size to use multiple 2k chips. Who knows, maybe they originally planned for reserving a 8k area for RAM, but instead of single 8K RAM chip, or single 4K RAM chip, they settled for single 2K RAM chip, as the design allows to use a single RAM chip of any size.