Is I/O port 0xFE reserved on the eZ80?

Question

TL;DR

Following on from OmarL's comment, to the closed question, Why did the Spectrum Next choose Z80 on FPGA?:

But also, the eZ80 is not compatible with the ZX Spectrum because it uses port FE for its own purpose.

Does anyone have a reference for this?

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I have found links to the ZX Spectrum's use of 0xFE for I/O, 16K / 48K ZX Spectrum Reference, but nothing for the eZ80 and its reserved use of 0xFE.

I did find a link to the ZX Spectrum SE Reference, which mentions the eZ80 in passing:

If you got very excited when Zilog announced the eZ80 then you should keep an eye on the development of Richard Kelsh's Sparky project. It uses its own 24-bit version of Basic, based in part on Sinclair Extended Basic. I thought I'd be the first to use Sinclair Extended Basic on genuine hardware but Garry Lancaster, designer of the ZX Spectrum +3e, beat me to it. I'm working with him to ensure Sinclair Extended Basic supports ResiDOS - the operating system of the ZXATASP IDE interface. We are also looking at the possiblity of merging aspects of the +3e and Sinclair Extended Basic.

as well as the familiar I/O use of 0xFE, but nothing regarding the port's use relating to the eZ80.

I would like to know if it is true that the eZ80 can not be used as a drop in replacement on the ZX Spectrum, due to a conflict relating to the port 0xFE issue.

Note: There may be other reasons why it can't be dropped in, but this question refers only to the 0xFE issue.

Answer 1

The CPU-CORE as described in the eZ80 User Manual (UM0077) does of course not reserve any I/O, but all real silicon eZ80 contain additional peripherals (*1), reserving the whole address range of 0080h..FFh for them.

See for example the eZ80190 Product Specification (PS0066) section Register Map on p.23:

All on-chip peripheral registers are accessed in the I/O address space. All I/O operations employ 16-bit addresses. The upper byte of the 24-bit address bus is forced to 00h (ADDR[23:16] = 00h) during all I/O operations. All I/O operations using 16-bit addresses within the range of 80h to FFh are routed to the on-chip peripherals; where xx is any value from 00h to FFh. External I/O Chip Selects are not generated if the address space programmed for the I/O Chip Selects overlap the 80h to FFh address range.

So yes, that address is locked.

Table 2 on page 28 marks for port 00FEh:

FE | DMA1_BC_H | DMA1 Byte Count Register—High Byte

To my understanding all eZ80 silicon not only feature a DMA unit at that address, but also stamp out the 80h..FFh ports by default, avoiding any external decode. The I/O cycle will simply be not visible.

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IIRC the FEh register controls cassette and border colour. For the ROM it might be rather painless to patch all occurrences to, for example, 7Eh, so everything BASIC not using direct hardware access will run. But that's about it. All other software will write into the DMA count and thus fail.

Now, if I/O cycles within 80h..FFh would be visible externally, it would be possible to decode it as well and treat the DMA register more like a parallel RAM cell. Except, the way the Spectrum is made, the ULA reacts to all even ports (yeah, cheap as always) and some software might use that knowledge, which could cause rather unwanted effects when hitting some of the other peripherals.

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*1 - Usually integrations of CTC, PIA, SIO (UART, SPI, I2C) and DMA, plus MAC and address decoder.

*2 - Cheap as always, which was the main feature of all Sinclair and why we got them in the first place. But unlike Commodore, where Tramiel killed usage of features to save on development cost, Sinclair did minimize on every bit of hardware.