The 6502, like many 8-bit processors, has a somewhat arcane opcode-mode restrictions. On most such processors, the restriction is a clear result of trying to pack a lot of instructions into a limited number of opcodes. On the 6502, however, the number of opcodes without a specified meaning is huge. Among other things, there are no defined opcodes at all whose bit pattern ends in 11.
Because the number of instructions that use any kind of memory operand is less than 24, and the number of instructions with only one addressing mode is less than 64, it would have been simple to say that all opcodes whose bottom two bits are not 00 are memory-format instructions, all of which would compute their addressing mode as specified by the next three bits. This would have been simpler than having different instructions compute addressing modes differently. On the other hand, it would have filled up most of the opcode space where the bottom two opcode bits are 11.
Is there any information about the design process that would indicate whether there was a deliberate design decision to leave unused the portion of the opcode map where the bottom bits are 11, and squeeze in opcodes where needed to accommodate that, or was the fact that that portion of the opcode map was unused merely design happenstance?