I came across an Intellivision in a box of stuff. When I looked it up on Wikipedia, it said that it uses a CP1600 that is based off a PDP-11. There's a weird entry on the wiki page:

CP1600 did not support memory-memory indirect addressing (offsets), and looping was implemented in a different way which allowed it to run much faster

This seems to be very different from a 6502 or 68k. Does anyone know if there was a modified looping method or is this entry just plain wrong?

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    After reading that wikipedia description of it, I seriously question what "based on the PDP-11" means. Sounds like "designers had read about the PDP-11, and one of them had programmed one in college, and sort of remembered what it was like, though he had been drunk most of those years".
    – davidbak
    Oct 5, 2021 at 2:01
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    @davidbak It looks "PDP-11 inspired" to me. But less orthogonal, and tighter instruction encoding because some of the registers have particular purposes. And IIRC you can use either 16-bit bus or 10-bit bus for the program data which is kinda bizarre. Oct 5, 2021 at 8:19
  • @OmarL It's not more PDP-11 inspired than any other CPU with 8 registers of which are SP and PC are two. The 10 bit instruction format is a very CDP1600 specific thing thoough.
    – Raffzahn
    Oct 5, 2021 at 10:14
  • Other things they have in common: two-address instructions, the status flags being mostly the same in name/meaning, similar addressing modes, including post-increment and suchlikes. Unlike their (remote) predecessors, they have eschewed conditional skips for test-and-branch. Or maybe we could say, considering all of this, that both CP1600 and PDP-11 are both IBM-360 inspired :-) Oct 5, 2021 at 10:28
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    @OmarL - I don't see two-address instructions, if you require 'address' to indicate a location in memory. There's a 'mode' field for one operand, which is either a register or indirect through a register (= PDP-11 deferred mode, sort of), and only a 'reg' field through another, no capability to address memory.
    – dave
    Oct 5, 2021 at 12:34

2 Answers 2


TL;DR: No.

The CDP1600 did not have any unusual/speedy loop mode, but its predecessor, the DG Nova mini computer, had two very innovative and increment/decrement instruction, using a core memory feature for speedy execution that did improve counting loops.

Let's start with a basic misconception here:

it said that it uses a CP1600 that is based off a PDP-11.

No. It isn't. It is a far descendant of the PDP-8 - or more exactly, the PDP-X. The PDP-X was a skunkworks project lead by Edson de Castro to improve manufacturing density (*1) and move DEC's development away from their 6 bit line (PDP-8/9/10/...) toward an architecture based on multiples of 8 bit. A move not really seen as necessary by Ken Olsen who cancelled it in early 1968.

As a result Castro and some other engineers left DEC and founded Data General in 1968. The DG Nova was created, from idea to first customer delivery (Feb 1969), in less than a year. Due to improvements in PCB manufacturing as well as higher integrated chips from Fairchild, they could pack the whole CPU on just two boards instead of the several dozen Flip-Chip modules a PDP-8 needed. As a result a more capable Nova could be sold for 2/3 the price of a PDP-8 while being faster as well.

(IIRC) It was the first machine to use the famous 74181 ALU - later also applied by DEC for the PDP-11. The higher integration allowed more registers within the CPU, so the Nova had 4 accumulators instead of the one the PDP-8 had. Besides the PC, accumulators (register) 2 and 3 could be used for indexed addressing.

Over all, it's a simplified, more regular PDP-8, with added registers, built on much improved manufacturing technology.

The Nova was an instant success and turned the DG into an existential threat to DEC. Cheaper and more powerful. DEC had to create something to counter and Olsen had to rethink his stance about 8 vs. 6 bit. The result was the PDP-11, that premiered a year later. The PDP-11 was created with more than just one eye on the Nova and was made to outperform her in any way, quite visibly in a rich instruction set that included everything the Nova had plus more.

DG countered this not much later with the improved SuperNova in 1970, increasing speed to over 3 MHz, this being one of the fastest minis for several years(*3). Still, the way richer instruction set of the PDP-11 did make the SuperNova look inferior and eat into potential sales.

To over come this, the greatly enhanced Eclipse was introduced in 1974. Initially bug ridden and late, pushing many customers away. By 1976 the issues were resolved and due to the straight upgrade path a good sell.

But DEC already moved toward 32 Bit with the VAX series in 1977 which DG tried to counter with the somewhat overblown 32 bit Fountainhead project, which never reached maturity - but lucky there was the Eagle, a skunkworks project (history is a bitch ;)) by a few Nova engineers who believed in making good things better. Released in 1980 as Eclipse MV/8000.

That battle is immortalized in Tracy Kidder's book The Soul of a New Machine

The micro part of history continues before that with

  • National's IMP-16 of 1973 which is a bit slice implementation quite close to the DG Nova.

  • National's PACE (and its less faulty cousin INS8900) of 1974 is a single chip implementation of the same architecture, now augmented with a 10 entry on-chip stack - Like the Eclipse and later the Nova 3

  • And finally there is the CDP1600 series of General Instruments of 1975, a greatly enhanced version of the Nova Architecture, but not binary compatible (kinda like 8086 vs. 8080)

  • DG created as well a single chip Nova, the microNova, but too slow and too late (1977) to really compete - by the time the microNova design was mature, the IBM PC started to take over the low end market.

The CDP1600 had the original 4 accumulators of the Nova/PACE (with AC1 as well usable for addressing) plus two more for addressing with auto increment and a 'regular' stack pointer and the PC integrated as addressable registers (R6/R7). Unlike its predecessors the address part of an instruction is 16 bit instead of 8, allowing absolute addresses as well as +/- 32 KiB addressing range.

Bottom line: CDP1600 is an extended Nova architecture.

It seems that the presence of 8 registers, with SP and PC being number 6 and 7, did mislead the author to assume a PDP-11 linage. One of these misconceptions that spread so easily around the net.

This seems to be very different from a 6502 or 68k.

Not sure what these CPUs should mean in relation, as both are even less related to a PDP-11 (or a CDP1600).

Does anyone know if there was a modified looping method or is this entry just plain wrong?

No, not really. But the CDP1600's predecessor, the Nova did introduce two instructions, ISZ/DSZ to increment(*4) or decrement a (16 bit) memory word. They were special as the counting was executed by a dedicated adder within the memory (*4), making them not only atomic and fast, but extreme fast as well (*5). Using them, loops were possible without the need to use a register for counting, 'wasting' time to load and store the counter for each handling. This did improve looping quite a lot compared with the PDP-8, but not the PDP-11, which added the same feature (*6).

By the time of the CDP1600, core memory was history , these instructions are nothing special anymore, not different from any other CPU that allowed to increment/decrement a memory word.

What is special about the CDP1600 was the Branch External instruction (BEXT), a relative branch conditioned on external hardware. When a BEXT is executed, a 4 bit branch code is put on dedicated pins and external hardware can react with a response signal if the jump is to be taken or not. This can be used to check one of 16 external conditions, quite handy with external coprocessors (which there are other preparations are made as well) or in control application ... like a video game :))

Long story short:

  • No, it is not based on a PDP-11. There are some rather generic similarities, but they are rather far fetched and mostly due a similar assembly language - originated in their common ancestor the PDP-8. So if at all, then the PDP-11 would be the one inspired here :))

  • No, the CDP1600 had no loop improvement. Its counting instruction was like many other CPUs had.

Much like Davidbak, I would as well see that sentence as a less than professional opinion.

*1 - This was the late 1960s, where chip and board manufacturing density increased in almost monthly intervals.

*2 - Addressing modes were Zero Page, PC relative, R2/R3 relative.

*3 - IIRC it was also the first machine where ROM was not only a feature, but a massive speed improvement. Operating from ROM the machine was about 2-2.5 times faster than with the same code in core.

*4 - For everyone crying "But the PDP-8 did this already with ISZ and Autoindex !!!111!!!".

Yes, the PDP had an incerementer (not an adder) within the memory controller that worked whenever location 8..15 was used for indirect addressing. It was neither for generic counting nor could it decrement. It was a very specific and rather limited feature, only dedicated at string operations. Additional use, like as a stack pointer did already need several additional instructions working around this. Likewise is only having ISZ rather cumbersome for making a loop counter. The Nova is simply the next generation PDP-8 removing many limitations.

*5 - It's helpful to remember that the Nova did use core memory and core memory is based on destructive read. Data read has to be written again, usually done by the memory controller, hidden from the CPU.

The ISZ/DSZ design used this drawback as an advantage by routing its data word thru a dedicated adder, located within the memory write logic, the before write back. The new value is what was transferred to the CPU, so tests for zero could be done right away. This folded the otherwise needed instruction sequence of reading, incrementing, writing and testing into a single read like instruction, making a counter in memory (almost) as fast as if kept in a register.

So, if anyone tries to tell a story about 'Computational RAM' being the newest invention, just point him back to the DG Nova in 1969.

The CDP1600 lost that advantage, as it uses regular semiconductor RAM, so the adder is within the CPU, like with any other CPU.

*6 - Always keep in mind, the PDP-11 was created as reaction to the incredible success of the DG Nova, so it had to offer everything the Nova did - and more.

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    Excellent details. (I myself never ever used any DG hardware. I guess I was a Digital fanboy (before the term was invented). Even purchased a Rainbow 100 on my own.) Are ISZ/DSZ related to the PDP-8 "auto-increment-if-indirected-through" addresses, but generalized to all of memory instead of 8 (?) specific locations?
    – davidbak
    Oct 5, 2021 at 4:09
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    Why does the CP1600 operate faster from ROM? (I am asking about your footnote 3) Oct 5, 2021 at 11:41
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    @OmarL Footnote 3 is about the SuperNova (My write up is more about history than the CDP1600, as the origin is what the question is about). She used core memory with a cycle time of 800 ns as RAM. but could as well take boards with brand new semiconductor ROM (keep in mind, having ROM was rather unusual at the time) operating at 300 ns. so about 2.5 times the speed.
    – Raffzahn
    Oct 5, 2021 at 12:08
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    Nice essay, but the question is about branches, which really ought to take centre-stage in the answer :-)
    – dave
    Oct 5, 2021 at 12:27
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    The Nova did introduce two unusual instructions, ISZ/DSZ to increment or decrement a memory location - The ISZ instruction was introduced by the PDP-8. The NOVA copied it and added the counterpart DSZ. Oct 5, 2021 at 15:55

"Just plain wrong".

There's a "branch on condition" instruction (one word) that uses the condition codes to decide whether to branch.

The branch target is stored in a second instruction word, as an offset (plus/minus) from the program counter.

If that's "faster", it's only faster than whatever they didn't implement. Maybe that alternative would have been to use the same register-based methods that are used for computational instructions. i.e., either the target address would have to be in a register, or the target address would have be in a memory word addressed by a register.

The manual. Section 3.2.2 for conditional branch instructions.

It's clear by the way that the designer has seen a PDP-11, but it's not very much like one. The instruction format contains a 3-bit mode and a 3-bit register number (but only one mode/reg pair, not two as per PDP-11). But they're used in a funny way: the mode implies one of the registers used in the operation (so a CP1600 "mode" is like a PDP-11 "mode and reg"), and the register is the other operand. Not nearly as clean as the -11.

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    "It's clear by the way that the designer has seen a PDP-11, but it's not very much like one." I believe the Nova was released before the PDP11 so it is possible it is the other way round -- the PDP 11 borrowed features from the Nova.
    – ghellquist
    Oct 6, 2021 at 18:06
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    I don't think so. The PDP-11 design is rather unique, and came out of CMU, from Gordon Bell and Harold McFarland. It's the modes-and-regsters combo which makes the difference. Prior to what we actually got, there was an earlier design that was rejected as being (my description) too boringly like every other mini out there.
    – dave
    Oct 6, 2021 at 19:33
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    @ghellquist - I just read up on the Nova; the PDP-11 is not at all like it. Nova is basically a load/store architecture; arithmetic/logical operations only in registers; limited addressing modes; not-really-general registers, and so on.
    – dave
    Oct 6, 2021 at 21:36

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