Other answers note that most SID chip registers are write-only, but didn't really go into why.
When connecting storage elements to a bus, separate circuitry is required to read and write them. If a device has many storage elements whose state need not be made available to outside electronics (as would be the case for a RAM), all of the storage elements can be placed close together and each equipped with a "select" signal, and one can then use a single set of read circuitry and a single set of write circuitry to handle accesses to the entire array. If the state of each storage element needs to be forwarded continuously to outside circuitry which is supposed to do something with it, however, practicality will often dictate that each storage element be placed near the circuitry it controls, which would effectively preclude the sharing of read-write circuitry. Some devices attach read-write support circuitry to every register, but in the 1980s where signals generally had to be routed between active circuits rather than over them, the cost of doing so would have often been significant. Some device designers tolerated the cost, while others avoided it.
In some ways, the selection of read registers on the SID is a bit surprising. If the SID had included a simple software-controlled DAC that would be mixed with the final output, along with a single-bit analog comparator to determine if the output with the DAC mixed in was above or below a particular threshold, a single-bit read register from the analog comparator would have made it possible to write a software-only test program that could confirm the functionality of everything else out to the final output amplifier stage. If e.g. one of the bits in the channel 1 frequency output control wasn't working, a test program could recognize that the SID wasn't producing the correct pattern of highs and lows coming back on the comparator. From what I can tell, the SID's readable registers would be insufficient to determine whether any of the channel 0 and channel 1 registers are working.
I suspect that the readback feature for channel 2's output was intended for use in chip development, so that if the channel hardware design had a problem it would be possible to see what was going on. If e.g. the carry chain in the frequency generation circuitry was unreliable, being able to program a sawtooth wave and watch whether the values count in consistent order would be easier than trying to figure out what's going on based upon the output signal alone.
Further, if the designers of the SID had more time available, they could have saved chip area by using a time-shared architecture which would have used the same circuitry to read and write the registers from all four voices. This would have reduced the amount of circuitry required to support full readback of all registers, thus making it more likely that readback would be supported. Indeed, depending upon the design chosen, the simplest way to allow registers to be updated at arbitrary times in a time-sharing system might have been to use a small RAM to hold them, and have on-chip logic use half of each system clock cycle to read the settings for the current voice and half of each cycle to expose the RAM to the CPU. Getting such a system working, however, would probably have required more effort than getting a single-voice tone generator working and plopping on the chip as many copies as would fit, and given the time constraints that wasn't practical.
