# Have there been any instruction sets with an odd register width?

Did any early instruction sets have an odd integer register width? The reason I am asking is because all of the instruction sets I have read about (on this site and elsewhere) have had an even general purpose register width, if not a power of two. I do not see a reason why this has to be so. Am I missing something? If so, could someone explain it to me?

• The register width of the MC14500B is odd and a power of two. Commented Nov 1, 2021 at 0:55
• Does the Itanic with its uninitialized-bit or whatever count? :-) Commented Nov 1, 2021 at 23:42
• There is a discussion in the comments of phuclv's post about it. Commented Nov 1, 2021 at 23:43
• If PC counts as a register, then see retrocomputing.stackexchange.com/questions/12794/… -- there may be other Microchip PICs with weird word sizes Commented Nov 2, 2021 at 15:42
• Do you mean odd as in unusual, or odd as in 2n+1? Commented Aug 4, 2022 at 7:19

Below are some architectures with odd word sizes:

Note that the register size may be a multiple of the word size, because many early computers allow subdividing the register into multiple components

Another more recent example is Itanium which has 82-bit floating-point registers and 65-bit general-purpose registers. One bit in the GPR is a trap bit called NaT (Not A Thing) rather than a value bit. In reality NaT works almost the same as NaN in floating-point by propagating errors and allowing arithmetic operations to work normally on software-speculated load results, without checking until the final result

All mathematical operations on NaT just produce NaT again.

Uninitialized garbage on ia64 can be deadly

The important thing to know about NaT right now is that if you take a register which is tagged as NaT and try to do arithmetic with it, then the NaT bit is set on the output register. Most other operations on registers tagged as NaT will raise an exception.

The NaT bit means that accessing an uninitialized variable can crash.

``````void bad_idea(int *p)
{
int uninitialized;
*p = uninitialized; // can crash here!
}
``````

The Itanium processor, part 1: Warming up

• Note that the AGC accumulator A and return address register Q are 16 bit.
– WimC
Commented Oct 31, 2021 at 6:48
• Are all 65 bits accessible to software in the same manner on Itanium? Commented Oct 31, 2021 at 8:53
• @Ruslan yes, software can check that NaT bit easily The Itanium processor, part 7: Speculative loads Commented Nov 1, 2021 at 3:19
• @Ruslan yes but arithmetic instructions can accept it and work somewhat similar to NaN in floating point so you don't need to use `chk.s` separately Commented Nov 1, 2021 at 10:13
• Itanium also has 41-bit instructions (grouped into 128-bit bundles containing three instructions and a 5-bit code to indicate instruction types). Commented Nov 2, 2021 at 15:34

The EDSAC (started in 1947) had been intended to have 18-bit words, but due to timing difficulties in the mercury tanks, it ended up with only 17 (= 18 - 1) bits usable for word operations, or 35 (= 2 x 18 - 1) bits for double word operations. True, this was "memory" and not "registers", in modern but not contemporary parlance.

Internally, the EDSAC used two's complement, binary numbers. Numbers were either 17 bits (one word) or 35 bits (two words) long.

The major register (in the modern sense) was the accumulator. This too had an odd length.

The accumulator could hold 71 bits, including the sign, allowing two long (35-bit) numbers to be multiplied without losing any precision

Wikipedia

The EDSAC was a serial machine (i.e., 1-bit ALU)

In summary, there is no reason why word length needs to be even or a power of two. In the heroic era, every bit added to the system cost, so you had the minimum that you needed. These days, the 8-bit byte and forward and backward compatibility are the drivers. Thus 64 bits was the logical follow-on to a 32-bit 'standard' word size.

• “due to timing difficulties in the mercury tanks” — I love this site Commented Nov 2, 2021 at 15:04

The Elliott 803 computer was 39-bit.

The instructions are 19-bit with two per word plus a single bit modifier for the remaining bit.

Elliott 803 Wikipedia

• Our Computer Heritage link. The earlier 802 had a 33-bit word.
– dave
Commented Oct 31, 2021 at 0:18
• Technically, the question is asking about register length, which I assume is meant in the modern sense (though in the UK in the 1940s and1950s, a "register" was a word in memory). The 803 accumulator was 33 bits,
– dave
Commented Oct 31, 2021 at 0:57
• @another-dave - Are you sure? The instruction timings on the Computer Heritage website are consistent with the 803 having a 39 bit accumulator compared to the 33 bit for the 802. Commented Oct 31, 2021 at 16:56
• Hmm, I think I must have read 802 and written 803. I can't now tell whether it was a simple typo or mental fog, but a 39 bit word and a 33 bit acc doesn't make a lot of sense.
– dave
Commented Oct 31, 2021 at 17:34
• Nice. An odd length accumulator, and odd length instructions. I was going to mention the 503 until I saw your post. Commented Jan 26 at 8:00

To touch on the underlying question:

I do not see a reason why this has to be so.

There is none.

Register width is selected for 3 basic reasons:

• Fitting the purpose by being able to hold (usually overlapping)
• the most important data type, or
• the most basic data type, or
• a memory word.
• Fitting (CPU) building elements, by being multiples of
• ALU element sizes used, and
• data bus sizes used
• Fitting off-the-shelf components like
• memory module width (eventually most important)
• system or I/O bus size.

For example, 12/18/36 bit register sizes/architectures were much promoted during the early 1960s due to availability of off-the-shelf core memory modules 18 or 36 bits wide. Core was the most expensive component at the time, so being able to buy a ready-made one saved a lot of development cost (*1). Not to mention that reusing existing models increased the usability.

Of course there is a symbiotic relation between the later two and register size selections, as such components were made to fit common register sizes - the early prevalence of 4 bit wide semiconductor ALU and memory components was a direct result of them fitting 4/8/12/16 bit architectures. In turn this promoted the further dominance of 8/16/32 bit ISA.

*1 - This may sound strange, considering that core was made in stacks of bit-planes, so any bit width could easy be produced by adding the wanted number of planes. Except a core module is not just buying the stack, but its control logic as well. Using a non-standard word width results in the need to develop type-specific control logic. And while the engineering may be a no-brainer, it does incur higher design and manufacturing cost than buying off-the-shelf sizes.

• I think that's what you were intending to say. Feel free to change it if I misread. Commented Oct 31, 2021 at 10:13
• @AlexHajnal Thanks for looking, bu not really. In both cases. Core was not easily, but (almost) always the most expensive component. a) A core stack (of reasonable) size was more expensive than the same amount as drum. b) and while it's true that it's good idea to reduce the number of modules, it comes second to the fact of buying of the self modules (not just stacks) at all. Let me add a footnote here. Commented Oct 31, 2021 at 10:24
• re so not being able to buy one saved a lot of development cost I'm not sure what this is trying to say. "Being able to buy one (off the shelf) saved costs"? "Being able to not buy one (=not needing to buy more planes) saved costs"? I suspect the former is what you meant.
– dave
Commented Oct 31, 2021 at 11:40
• @another-dave Yeah, double edited and still screwed :)) Commented Oct 31, 2021 at 16:03

Great historical examples here, but I missed the one-bit slice processors that were developed in the 1970-s, that went on to the (Intel) four-bit and 8-bit processors that are better known.

One (1) is the (ultimum) oddest number for CPU register size, you can't go much lower, while the current craze is to crunch as many bits at a time as possible.

Examples:

For more recent architectures, you might take a look at quantum computers. If you think about it, it is not the bit-width of the registers, but the cleverness of the algorithm that makes computers able to do useful work. More bits may mean more speed. But because quantum bits are so difficult to make, people found ways to do useful work with very low number of quantum bits, hence probably also with odd numbers, or even one bit.

Note that back then, a single bit was also not that cheap to make. Thats why early processors had low bit numbers like 1, 4, or 8, hence not necessarily even numbers or exact powers of two.

• "Ultimum"? I only find that in a Latin dictionary. Commented Nov 2, 2021 at 15:38
• Probably meant "ultimate". Likely without knowledge of Latin, as otherwise, we'd use "principal" or similar. I don't know Latin, but IIRC, "ultima" is furthest, whereas "prime"/"principal" are about being first. Commented Nov 2, 2021 at 17:29
• The 2901 isn't really a processor. It's a 4-bit wide ALU Commented Nov 3, 2021 at 2:14
• @TobySpeight "excuse my french", I indeed meant something like ultimate, and updated my answer Commented Nov 3, 2021 at 10:36

If you are into art, you may have heard of the MIX computer from The Art of Computer Programming.

Its words are 5 bytes (not like any other architecture's bytes) plus a sign. So are registers `A` and `X`. When implemented in bases 4 and 64 to 100, each byte has an odd number of bits.

• This answer refers to "Knuth". Once so well known that no further reference to wikipedia or whatsoever was needed Commented Nov 3, 2021 at 10:41
• I like the "into art" phrase. My long-standing position is that the single most important quality for a programmer is "good taste".
– dave
Commented Nov 3, 2021 at 12:38
• Knuth revised MIX later into MMIX (has 256 general-purpose 64-bit registers that each can hold either fixed-point or floating-point numbers so not relevant for this). Commented Aug 4, 2022 at 16:03
• @ThorbjørnRavnAndersen: Not so much "revised" as "replaced". Commented Aug 5, 2022 at 22:03

Zuse Z22 from 1955 (one of the first computers built in series) had 38 bit wide architecture with 38 bits wide registers.

https://en.wikipedia.org/wiki/Z22_(computer)

edit: upps, you meant odd like in "not divisible by 2", my bad, I understood it as odd like in not common.