Did any early instruction sets have an odd integer register width? The reason I am asking is because all of the instruction sets I have read about (on this site and elsewhere) have had an even general purpose register width, if not a power of two. I do not see a reason why this has to be so. Am I missing something? If so, could someone explain it to me?
Below are some architectures with odd word sizes:
- Apollo Guidance Computer: 15-bit
- Autonetics D-37C Minuteman II Guidance Computer: 27-bit
- Electrologica X1, Electrologica X8: 27-bit
- Calcomp 900: 9-bit
- Gemini Guidance Computer: 39-bit
Note that the register size may be a multiple of the word size, because many early computers allow subdividing the register into multiple components
Another example is Itanium (not quite early as in the body but fits the question title completely) which has 82-bit floating-point registers and 65-bit general-purpose registers, although one bit int the GPR is a trap bit called NaT and not a value bit
See also Did any computer use a 7-bit byte?
The EDSAC (started in 1947) had been intended to have 18-bit words, but due to timing difficulties in the mercury tanks, it ended up with only 17 (= 18 - 1) bits usable for word operations, or 35 (= 2 x 18 - 1) bits for double word operations. True, this was "memory" and not "registers", in modern but not contemporary parlance.
Internally, the EDSAC used two's complement, binary numbers. Numbers were either 17 bits (one word) or 35 bits (two words) long.
The major register (in the modern sense) was the accumulator. This too had an odd length.
The accumulator could hold 71 bits, including the sign, allowing two long (35-bit) numbers to be multiplied without losing any precision
The EDSAC was a serial machine (i.e., 1-bit ALU)
In summary, there is no reason why word length needs to be even or a power of two. In the heroic era, every bit added to the system cost, so you had the minimum that you needed. These days, the 8-bit byte and forward and backward compatibility are the drivers. Thus 64 bits was the logical follow-on to a 32-bit 'standard' word size.
The Elliott 803 computer was 39-bit.
The instructions are 19-bit with two per word plus a single bit modifier for the remaining bit.
To touch on the underlying question:
I do not see a reason why this has to be so.
There is none.
Register width is selected for 3 basic reasons:
- Fitting the purpose by being able to hold (usually overlapping)
- the most important data type, or
- the most basic data type, or
- a memory word.
- Fitting (CPU) building elements, by being multiples of
- ALU element sizes used, and
- data bus sizes used
- Fitting off-the-shelf components like
- memory module width (eventually most important)
- system or I/O bus size.
For example, 12/18/36 bit register sizes/architectures were much promoted during the early 1960s due to availability of off-the-shelf core memory modules 18 or 36 bits wide. Core was the most expensive component at the time, so being able to buy a ready-made one saved a lot of development cost (*1). Not to mention that reusing existing models increased the usability.
Of course there is a symbiotic relation between the later two and register size selections, as such components were made to fit common register sizes - the early prevalence of 4 bit wide semiconductor ALU and memory components was a direct result of them fitting 4/8/12/16 bit architectures. In turn this promoted the further dominance of 8/16/32 bit ISA.
*1 - This may sound strange, considering that core was made in stacks of bit-planes, so any bit width could easy be produced by adding the wanted number of planes. Except a core module is not just buying the stack, but its control logic as well. Using a non-standard word width results in the need to develop type-specific control logic. And while the engineering may be a no-brainer, it does incur higher design and manufacturing cost than buying off-the-shelf sizes.
If you are into art, you may have heard of the MIX computer from The Art of Computer Programming.
Its words are 5 bytes (not like any other architecture's bytes) plus a sign. So are registers
X. When implemented in bases 4 and 64 to 100, each byte has an odd number of bits.
Great historical examples here, but I missed the one-bit slice processors that were developed in the 1970-s, that went on to the (Intel) four-bit and 8-bit processors that are better known.
One (1) is the (ultimum) oddest number for CPU register size, you can't go much lower, while the current craze is to crunch as many bits at a time as possible.
Motorola MC14500B http://www.righto.com/2021/02/a-one-bit-processor-explained-reverse.html
For more recent architectures, you might take a look at quantum computers. If you think about it, it is not the bit-width of the registers, but the cleverness of the algorithm that makes computers able to do useful work. More bits may mean more speed. But because quantum bits are so difficult to make, people found ways to do useful work with very low number of quantum bits, hence probably also with odd numbers, or even one bit.
Note that back then, a single bit was also not that cheap to make. Thats why early processors had low bit numbers like 1, 4, or 8, hence not necessarily even numbers or exact powers of two.
Zuse Z22 from 1955 (one of the first computers built in series) had 38 bit wide architecture with 38 bits wide registers.
edit: upps, you meant odd like in "not divisible by 2", my bad, I understood it as odd like in not common.