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I am working with a W65C02S chip and it has extra opcodes, BBRn and BBSn that branch on a bit set, or bit reset. However, I cannot find on which register or memory location this check is done.

When looking for more info on these opcodes, I found this from 6502.org. But that is talking about an extra addressing mode zp,rel, which is not talked about at all in the W65C02S datasheet. The datasheet says these opcodes use the r (relative) addressing mode.

I would assume BBRn/BBSn use the accu, but can someone confirm?

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  • I would assume the addressing mode in the datasheet is wrong. The datasheet (this one?) and the linked 6502.org page describe the exact same opcode bytes, but since the datasheet doesn't describe the actual opcode operation, I guess this is where an error might have snuck in.
    – user3840170
    Nov 6, 2021 at 12:54
  • Seems like it yes. When single stepping the code on the actual chip I can see it reads from the zero-page the address I programmed it to jump to (probably to load it to check the bit).
    – Bart Friederichs
    Nov 6, 2021 at 13:13
  • Appendix C ("The Rockwell 65C02") in the Eyes/Lichty 65816 book explains the BBR and BBS instructions. They take two operands, which is unique in the 6502/65C02 instruction sets; the only other instructions in the classic 65xx CPUs that take more than one operand are MVN/MVP on the 65816. (This was sort of annoying for me... my disassembler makes some assumptions about there only being one operand. Whoops.) As noted in the data sheet, the operands are a ZP address and a relative branch offset. Some 65xx offshoots have even more expansive instructions, e.g. some HuC6280 ops take three.
    – fadden
    Nov 7, 2021 at 0:17

1 Answer 1

Reset to default
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This documented appendix from WDC that describes how to use macros to replace these instructions (e.g. for the W65C816) provides the following equivalent set of instructions for BBSn PAGE0_BYTE, BITnSET:

   PHP
   PHA
   LDA PAGE0_BYTE
   AND #BIT_n
   BEQ L1
   PLA
   PLP
   BRA BITnSET
L1 PLA
   PLP

From this, I would conclude the 8 BBSn opcodes take a two byte operand. The first byte uses zp addressing to identify the byte that is tested, and the second byte is the relative address of the branch target. BBRn works the same way.

Better/simpler documentation is available publicly. The "new addressing mode" is described there as:

a combination of zero page addressing and relative addressing -- really just a juxtaposition of the two

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  • 2
    Thanks, that clears it up. Quite interesting also that the data sheet completely misses an (new) addressing mode.
    – Bart Friederichs
    Nov 6, 2021 at 14:47

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