The first programmable, electronic, general-purpose digital computer, ENIAC had a "square rooter":
five of the accumulators were controlled by a special divider/square-rooter unit to perform up to 40 division operations per second or three square root operations per second.
Some later architectures, PDP-11 for instance, did not include the square root instruction in its floating point instruction set, only FADD, FSUB, FMUL, FDIV.
What was the first architecture with a hardware divider which did not include a square-rooter (and what was the software implementation of the square root function, if known)?