How does the serial port on the RC2014 get addressed?

Question

I see on the schematic that /M1 and A7 go to CS0 and CS1 respectively. As I recall, both of these need to be high for the chip to be selected. And A6 goes to CS2, which needs to be low for the chip to be selected.

And of course, /IORQ is inverted by the 7404 and fed into E, which enables the chip only when the Z80 is accessing the I/O address space.

As I understand, this scheme maps all I/O addresses in the range 0x80 to 0xbf to the serial port. But what is the involvement of the /M1 signal here? From what I understand, that basically disables fetching opcodes from the serial port. But the Z80 can't do that anyhow.

I'm asking about this because I'm designing a computer around the RC2014 micro and I want to understand whether I can narrow this range down any. For this reason it would be good to also know which address is actually used by the Microsoft BASIC and Monitor ROMs that ship with the RC2014.

Answer 1

As I understand, this scheme maps all I/O addresses in the range 0x80 to 0xbf to the serial port.

True

But what is the involvement of the /M1 signal here? From what I understand, that basically disables fetching opcodes from the serial port.

Again true (if that is somehow made possible at all). But it also protects the ACIA against falsely seeing an interrupt acknowledge as access.

But the Z80 can't do that anyhow.

Not fetching, but creating a combination of /M1 and /IORQ does happen during interrupts as active M1 and active IORQ signals an interrupt acknowledge cycle. Incorporating /M1 disables that the ACIA could feel accessed by some random value during such.

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Insert: Interrupt Acceptance and Acknowledge

Interrupts are only recognized during an M1 cycle when accepted, two states are inserted after T2. The manual calls them wait states, but in reality it's an I/O access marked by /IORQ - except, no I/O address will be outputted. Devices have to detect the combination of /M1 (which is still held active, as we're still within machine cycle M1) and /IORQ as interrupt acknowledge and request for a vector (there is also no active /RD present).

This is already mentioned with the signal description on page 7 and 8 of the 1977 technical manual (*1):

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I'm asking about this because I'm designing a computer around the RC2014 micro and

Cool.

I want to understand whether I can narrow this range down any.

In that case it's more about the software. As you mentioned,

• the ACIA will answer on any port pair between 080h and 0BEh.
• Is there an 'official' address, like 080h/081h, defined?
• Or are there guidelines suggesting that?
• Does existing software adhere to these guidelines?

After all, compatibility might be only of concern if your intention is to run existing software, written for the RC2014 without any modification. If this is not a goal, you're free to use any other address (in that case I'd suggest to go for full 16 bit decoding).

• Or is the 'knowledge' of this addresses confined to a few drivers or BIOS like routines and not (direct) used by other programs?

This would as well enable a better decoding, as you'd need to only patch/extend these drivers/BIOS routines to comply with your narrowed address range.

For this reason it would be good to also know which address is actually used by the Microsoft BASIC and Monitor ROMs that ship with the RC2014.

Well, unless there are fixed guidelines, noone may guarantee anything. So, as usual, a grep thru sources is your friend :))

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*1 - The first stop, whenever in doubt about some signals, must be the data sheet page describing them. It will usually support previous assumption, or sometimes, really only sometimes, offer a complete new view :))

Next step that would be looking for timing diagrams. They are especially useful when it's about device addressing modes like here (for this case see p.16 of the 1977 technical manual).

Both sections are usually present in all data sheets and quite prominent in manuals.

Answer 2

The schematic is slightly confusing as the typical notation for active low signals are left out.

The UART or ACIA is enabled with E high only during IO cycles, so when IORQ is low.

Read/write is defined by RW pin, write being low and read being high.

The UART needs CS0 and CS1 high, and CS2 low to be selected. Which means A7 must be high, and A6 must be low, and M1 must be high.

M1 will be low with IO read active during an interrupt acknowledgement cycle. Thus requiring M1 to be high will ignore interrupt acknowledge cycles and ACIA will only respond to actual IO read cycles.

The IO bus address will be 0b10xxxxxy, which means that the ACIA will respond to all addresses between 0x80 and 0xBF. As address bit A0 is connected to register select pin RS, all even addresses go to control/status registers, and all odd addresses will go to transmit/receive data registers.

As the address decoding ignores 5 bits, the two ACIA registers appear 32 times in the 8-bit address space.

Commonly a program would ever use two addresses at the base of the area to access the chip, so those addresses would be 0x80 for control/status and 0x81 for data.