I'm planning out a protocol bridge between ZX Spectrum clone system bus and an FPGA-based extension device. I am considering adding bus request/acknowledge support for DMA purposes, but reading "Z80 CPU User Manual" pdf (UM008011-0816) I see a discrepancy in the descriptions.
The description of pins does not state the /RFSH pin is tri-state:
RFSH. Refresh (output, active Low). RFSH, together with MREQ, indicates that the lower seven bits of the system’s address bus can be used as a refresh address to the system’s dynamic memories.
But the waveforms in "Figure 8. Bus Request/Acknowledge Cycle" suggests /RFSH pin goes floating.
Is this really a mistake in the figure? The doc surely has lots of other typos (mainly in opcodes).
I don't really depend on the /RFSH functionality to keep DRAM refreshed during long DMA cycles, the clone's video subsystem does refresh during its normal operation. But I'd prefer to be sure about actual behavior of /RFSH pin with respect to bus request/acknowledge cycle.