1

For one register of 6502 CPU (here X Index register) :

enter image description here

If the SB/X (load) signal and X/SB (bus enable) signal are both asserted at the same time, what happens ?

  1. X Index register take the bus value
  2. Bus value take the X Index register
  3. Undefined and these signals should never be asserted at the same time
  4. Other ?

I imagine that when a load signal occurs on a register, another register must have its bus enable signal to rely them together but what happens in this case ?

1
  • Both 1 & 2: X=X ?
    – Erik Eidt
    Jan 5 at 17:35
3

If the SB/X (load) signal and X/SB (bus enable) signal are both asserted at the same time, what happens?

You mean beside the fact, that it would need a useful instruction based on that function?

Since read and write port are different, X would be loaded with itself. A quick look at the Visual6502 graphics seem to support that.

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