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I have heard several claims (in the comments on this question and answers) that asserting the D̅M̅A̅ signal on the Commodore C64 cartridge port will immediately take the CPU off the bus by deasserting its AEC line. How does it do this?

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    If it's any consolation, the TRS-80 effectively does the same thing. If you try to assert the BUSREQ pin, the logic tri-states out all of the CPU busses immediately, rather than waiting for the BUSACK signal telling the requester that the Z80 has, indeed, given up the bus. In fact, the BUSACK signal isn't even made available anywhere. Good times.
    – Will Hartung
    Commented Jan 10, 2022 at 6:24

1 Answer 1

Reset to default
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In all versions of the schematics from the Commodore C64/C64C Service Manual, the D̅M̅A̅ line proceeds from the cartridge port to:

  1. A 3k3 pullup resisistor.
  2. A 74LS08 AND gate with BA (a VIC signal) to CPU RDY.
  3. A 74LS08 AND gate with "system" (i.e., not CPU) AEC generating CAEC to the CPU's AEC pin.
    U27 U27 negative logic

Thus bringing DMA low will immediately bring low one side of the AND gate in 3 above, causing the output to be low and AEC to be deasserted on the CPU. (The VIC-II chip may also independently deassert CAEC from the other side of the gate; this is used for DRAM refresh, among other things.)

The implication here is that unlike just asserting RDY, which can safely be pulled low any time,¹ one must be very careful of timing when asserting D̅M̅A̅. The "deassert RDY and wait three cycles" strategy to avoid conflicting with CPU write instructions isn't available here; you must keep track of when the CPU is doing a write and avoid asserting D̅M̅A̅ during that time lest it disconnect the CPUs address lines while it's completing a write sequence.

¹ CSG NMOS 6500 Microprocessors (1985) data sheet, p.7: "If Ready is low during a write cycle, it is ignored until the following read operation."

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    At first I though the two illustrations of 74LS08 gates were of the gates for points 2 and 3, but they're actually two examples of the third point (from different schematic diagrams).
    – Kaz
    Commented Jan 10, 2022 at 6:04
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    One may safely use the approach of driving RDY low and assuming the CPU will release the bus within three cycles, but one would need to refrain from asserting /DMA during those three cycles.
    – supercat
    Commented Jan 10, 2022 at 15:57
  • @supercat Not on an (unmodified) C64, as far as I can see. The only connection to the CPU's RDY pin is the output of the gate in connection 2, which can only be brought low by asserting D̅M̅A̅, which will also disconnect the CPU's address bus per connection 3. (BA is connected to the other input of the gate in connection 2, but that's an output from the PLA.)
    – cjs
    Commented Jan 11, 2022 at 15:10
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    @cjs: Hmm... I guess I'd blindly assumed an external wire would be available to trigger RDY. A lot of bus connectors seem to make some curious decisions.
    – supercat
    Commented Jan 11, 2022 at 15:41

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