I understand the writing process to each core but how is reading accomplished?
By writing a zero and looking at the sense line:
- If that bit was a zero nothing happenes
- If that bit was a one a pulse can be sensed on the sense line.
After that the stored content is zero, that's why it's called a destructive read, so content needs to be written again.
Reading is essentially a combination of clearing the bit to read, reporting if a blip was seen (=1) or not (=0) and then writing it again. That's why each core stacks usually not only had dedicated amplifier logic, but also a register (one flip flop per plane) to hold what was read and logic to write it back without interaction of the host - much like later DRAM.
Do you have to measure the voltage on the sense wire and flip each of the bits while collecting the bits on the sense wire?
Because I feel if you flipped all the bits at once you would have several voltages just summed together.
Oh, I guess that's where you're stuck. What your picture shows is a single plane. Only one bit can be read or written at a time. To form bytes or words, several planes are stacked to form a ... well ... Stack (of core).
And yes, the plane seems to be four dedicated 64x64 sub-planes, but it does not allow a bit operation per sub-plane (working independently), as they use all the same X/Y lines. Any attempt to address two different bits in different sub-planes will also activate two mirrored bits (*1).
Then again, one can use this type of sub-plane to make a single board stack always writing(reading) the same bit in each sub-plane combining them to a 4-bit word (or 8-bit, if there's another 4 planes on the back).
This means activating the same row/column on each sub-plane. It still needs the same amount of drivers (one per X and Y line and plane, to be able to do 0/1 independently) but only one board with core. Very handy for small machines.
My memory pane is a 64K in size and has a front and back that are mirror and in parallel with the front. The sides have 4 windows and has 64x(s) and 64y(s) that I counted.
That doesn't really add up. 64x64 cores per sub-plane is 4,096 - with 4 of them on the front and back this adds up to 16,768 bits or 4 KiB.
How should I go about driving all these?
Well, you need a pair of drivers for all X and Y able to be switched per sub plane, 8 sense amplifiers to read and some logic to handle decoding and store the result in a register to be read by some consuming device.
Depending on your goal, this might be either a full figured parallel acting hardware, or a microcontroller with some decoders handling the 8 sub-planes in a serial fashion - which of course will be slower, at least for writing (2).
Personally I'd go with a microcontroller, a single adjustable write source and a set of CMOS multiplexers to 'scan' across the planes. Might be slower, but saves greatly on part count (*3).
*1 - Assume one writing bit 1;1 in the upper left sub-plane and 2;2 in the upper right, then bit 1;2 in the upper left and 2;1 in the upper right would also be written with the same value.
*2 - One can use 8 parallel inputs to read all 8 planes in parallel, while writing back in serial would be done only for ones, thus saving time.
*3 - Depending on circuit design one could interleave reading/writing the planes to some degree. Might be fun to fiddle with that :))