As a programmer I knew that on the C64 the CPU got the bus in the high phase of PHI2 and the VIC-II got it in the low phase and also stole extra high phases when required.
However, it wasn't until looking into the memory access timing diagrams that I became confused to as how this worked in practice. Specifically, as I understand the diagrams (and I accept I am probably wrong), the address lines need a certain amount of time to become stable before the rising edge of PHI2 and also the data bus needs some time after the falling edge to allow the DRAM to store the data on a write cycle.
If my understanding is correct, how does the VIC-II manage its access when some of the low phase is stolen by the CPU's requirements? (For background, I am trying to understand the DMA operation by an external CPU and how it respects the timing requirements)