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As a programmer I knew that on the C64 the CPU got the bus in the high phase of PHI2 and the VIC-II got it in the low phase and also stole extra high phases when required.

However, it wasn't until looking into the memory access timing diagrams that I became confused to as how this worked in practice. Specifically, as I understand the diagrams (and I accept I am probably wrong), the address lines need a certain amount of time to become stable before the rising edge of PHI2 and also the data bus needs some time after the falling edge to allow the DRAM to store the data on a write cycle.

If my understanding is correct, how does the VIC-II manage its access when some of the low phase is stolen by the CPU's requirements? (For background, I am trying to understand the DMA operation by an external CPU and how it respects the timing requirements)

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    Does this answer your question? What is the exact bus protocol used by the C64/C128 REU?
    – Brian H
    Mar 26, 2022 at 14:48
  • @BrianH Not really. It's a useful Q+A which I have been referrring to but it does not answer my specific query.
    – Robin Elvin
    Mar 26, 2022 at 15:09
  • Ah, so you aren't really talking about C64 DMA via the cartridge/expansion port, right? You want to know how to replicate exactly what the VIC-II does to access memory?
    – Brian H
    Mar 26, 2022 at 15:13
  • Yes, I am talking about DMA via the cartridge port since this is taking over from the 6510. I want to know what specific timings an external CPU needs to respect when performing read/writes to internal RAM. Unless it's as simple as PHI2 && BA Sorry if that isn't clear.
    – Robin Elvin
    Mar 26, 2022 at 16:30
  • It is (sorta) as simple as Phi2 and BA. Somewhat complicated by needing to know when it's safe to assert DMA in the first place and without stomping on a CPU write.
    – Brian H
    Mar 26, 2022 at 16:42

1 Answer 1

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First, it is helpful to recognize that the C64's VIC-II chip is more the "master" over the C64 system (address/data/memory) bus than the 6510 CPU. How is this so? The VIC-II doesn't just access the system bus. Rather, it controls the following CPU inputs directly- AEC, RDY, and the clock. This means the VIC-II directly mediates the access of the CPU to the system bus, and not the other way around.

This fundamentally turns the question of how to respect the system bus timing constraints on its head. Instead, the VIC-II design starts with the premise of the system bus timing being as prescribed by the VIC-II's own internal operation.

With the above in mind, it's a bit simpler to understand how the VIC-II prevents any bus conflicts or timing constraints. The VIC-II is just designed to run at a specified input clock (~8 MHz) , and leave enough margin in its generated outputs to the CPU to not violate the timing needed by the bus and memory chip components.

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