On this detailed 6502 block diagram that can be found all over the net, the increment logic for the high byte of the program counter is split into two 4-bit parts, with a named PCHC line for the carry from its low nybble to its high nybble.

What is the purpose of this split? I understand, of course, that with any multi-bit incrementer, you could claim any point is a "split", but notice that on that diagram, the low byte incrementer is not shown with a similar split: PCLC is the carry-out from the full 8-bit incremented value. And PCHC is a named line, suggesting it is used for something other than feeding into the high 4 nybbles.

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    Not posting as an answer because it's a complete guess, but maybe it's to do with carry look-ahead (some kind of wizardry which computes carry-out much faster). This might save some time on instructions streams that cross a page-boundary. Mar 28, 2022 at 13:20
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    What does the analysis of the chip itself say? It could be that the drawing is simplified due to space constraints.
    – UncleBod
    Mar 28, 2022 at 13:29
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    @UncleBod not really. While it misses some minor details (around control signals) it is astonishing correct for an abstract schematic. It really contains almost everything to understand or even recreate the CPU. Ofc, it saves a lot of brain power if one knows the micro code/PLA structure as well :))
    – Raffzahn
    Mar 28, 2022 at 13:51
  • Betting it has something to do with decimal mode.
    – LawrenceC
    Mar 29, 2022 at 14:42
  • @LawrenceC that's what I'd think, but this is the PC incrementer, not the general-purpose ALU I'm talking about.
    – Cactus
    Apr 1, 2022 at 12:20

1 Answer 1


TL;DR: It's all about speed.

Basic Ripple-Carry would take too long to perform a 16 bit increment at the desired clock rate (1..2 MHz), thus the PC increment was split and parts worked in Carry-Skip configuration.

More About Carry

Basic carry calculation (Ripple-Carry) requires the carry to propagate over all digits minus one. That is, each higher value bit stage has to wait for the previous before producing a valid carry. For an 8 bit value like all ALU operations, and the speeds a 6502 is designed for, it works out fine, but for 16 bits, as the PC needs, it would be simply too slow. So an improved incrementer (adder) design was needed for the PC, in this case a Carry-Skip design. Carry-Skip offers a faster response for a block at whole.

But Why Only PCH?

While Skip-Carry is faster, it does need more real estate. Thrifty as the 6502 designers were, they decided for a mixture of both. PCL is a basic propagating carry, while PCH is build as Carry-Skip. Their goal wasn't to create the performance wise best chip possible, but the smallest one good enough to do the job. That's the whole idea of the 6502: Make something barely able do the job, that could be sold for 1/10th the cost of a school book design.

So Why Not Carry-Lookahead?

Given, Carry-Lookahead is the eventually best solution - but also the most expensive. Doing Carry-Lookahead for a 16 bit counter needs more transistors than the incrementer itself. As before, the 6502 was all about minimizing the needed effort.

Is There More to It?

Yes, the PC incrementer is not only improved by using a partial Carry-Skip logic, but as well by inverting every other bit. In a school book Ripple-Carry the carry is created by a NAND gate producing an inverted carry and an INVerter to put it right again (*1). Having two stages adds two gate delays. By inverting every other bit prior to increment (and back again after) that inverter stage can be spared, thus speed penalty halved.

The speed gain is due the fact that before/after inversion is done in parallel for all affected bits, thus adding only two delay times in whole, while the inverters of a ripple carry work in series, adding 15 gate delays.

Is This Unique to the 6500?

No, quite contrary. It's a quite common way to improve without going full length. In fact, it's main rival, the Z80, had an even more interesting logic. It uses not only Carry-Skip, but in addition a Carry-Look-Ahead for its 16 bit generic in-/decrementer (*2). It's build from a series of two bit adders using Carry-Skip and a 7/5/3 bit Carry-Look-Ahead to speed up over all operation. Ken Shirriff did a nice analysis thereof.

A quite gerat design compromising between speed and real estate to deliver good performance. The 6500 design team dodged that task (*2) by optimizing all 16 bit operations away, except for PC increment. They created their own local optimum.

*1 - Yes, that makes it essentially just an AND gate, but in real life chips ANDs are shunned, as they are more complicate than NAND. But that's a different story, one about basic integrated electronics, so OT for RC.SE

*2 - The Z80, like it's predecessor 8080, had multiple 16 bit operations. There are, beside incrementing the PC and the refresh counter, a 16 bit stack pointer and 16 bit register pairs (HL, BC, DE, WZ) that used increment and decrement. Much like 6500's predecessor, the 6800, did for PC, SP, IX and A/B. The 6500 did away with all of this by reducing stack and indexing to 8 bit operation, to be done by the ALU. This left a single instance of fast 16 bit operation: incrementing the PC.

  • AND gates aren't necessarily problematic. While I know of no terminology for a generalized gate which combines an inverter with any combination of independent AND and OR gates on the input, in both NMOS and CMOS the cost of any such gate will be proportional to the total number of inputs, subject to normal fan-in caveats. If, for example, one needs not ((A and B) or (C and D)), one could implement that as ((A nand B) nand (C nand D)), but that would require six transistors for NMOS or twelve for CMOS, while the original function could be implemented with four or eight transistors.
    – supercat
    Mar 28, 2022 at 16:29
  • @supercat not sure what your point is. Are you arguing that AND can be provided with the same effort as NAND? Surprise it isn't, and that's the reason why AND are avoided.
    – Raffzahn
    Mar 28, 2022 at 17:50
  • An "AND" gate which needs to drive multiple outputs is expensive, but the particular scenario of an AND gate whose sole purpose is to drive one of the inputs of a NOR gate is cheap. Page 3 of the original Atari TIA schematic (NMOS design from 1977) near reference A5-6, for example, shows some such gates, and I wish there was a nice term for them.
    – supercat
    Mar 28, 2022 at 20:33
  • This means it's a signal line fully internal to the incrementer, right? there is no externally observable effect (other than the signal delay) from this setup?
    – Cactus
    Apr 1, 2022 at 12:24
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    @Cactus No, it's complete internal. Hansons diagram is the result of an analysis of the 6500 structure, thus he noted remarkable structures/design decisions. If it's about understanding/rebuilding with modern tools, the whole complex of PCxS/Incrementer/PCx can be seen as one unit. Of course, without showing the details it would be less easy to understand the play around the program counter during both clock phases :))
    – Raffzahn
    Apr 1, 2022 at 13:52

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