I've looked up PDP-11/70 handbook and it indeed has odd GPRs mapped to odd memory addresses (see page A-3 or 255 in reader's numeration).
But there's nothing wrong with it.
When the CPU accesses some memory location, it presents to the bus, basically, full byte address and access size (only word or byte in our case).
For real memory that consists of real bytes, or for real peripheral devices an attempted odd-address word access would present an unaligned condition: a hardware has to fetch two consecutive memory words and rearrange them as to present single unaligned result (same goes for peripheral accesses).
In a hardware that does not support unaligned accesses (like MC68000 or some modes of ARM Cortex-M3 CPU), such access causes a trap or exception.
Other hardware might decide to mimic such access as being aligned and return just the whole word at the previous even byte address (so does the K1801VM1 CPU).
However, when the access is made to the "virtual" part of I/O space (as soon as registers are actually not peripherals or memory), the decoding hardware might as well do as in PDP-11/70: byte address determines register number, and no byte-wise accesses to the registers are possible.
Another consequence of such grouping is a small economy of I/O address space which is already quite crowded in PDP-11s!