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The highest memory page in the PDP-11 series is the I/O-page. On some addresses devices can be accessed. Usually via words and they are also on even addresses. The cpu-registers are also 'visible' in that space and can be accessed there. Strange thing is though that R0 is on 177700 and R1 is on 177701 - an odd address!

My question now is: can all I/O-region be accessed both as word (16bit) and byte (8bit)? Not only the e.g. rk05 but also MMR0-3, the cpu registers, psw, etc.

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  • Which PDP-11 are you asking about? Within the PDP-11 family there is a lot of variety on this kind of detail.
    – Omar and Lorraine
    Mar 30, 2022 at 8:16
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    @OmarL The title says PDP 11/70
    – JeremyP
    Mar 30, 2022 at 9:20
  • There are two slightly different aspects to this: (1) the simple issue of whether you can do a byte access to an I/O address, transferring 8 bits, and (2) the rather strange case of the I/O space address of the CPU registers, which appear to have 'overlapping' word addresses but are nevertheless 16-bits wide and distinct. To the first "yes", though it might depend on the particular device. However, I know of no other example to the second part.
    – another-dave
    Mar 30, 2022 at 12:50

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I've looked up PDP-11/70 handbook and it indeed has odd GPRs mapped to odd memory addresses (see page A-3 or 255 in reader's numeration).

But there's nothing wrong with it.

When the CPU accesses some memory location, it presents to the bus, basically, full byte address and access size (only word or byte in our case).

For real memory that consists of real bytes, or for real peripheral devices an attempted odd-address word access would present an unaligned condition: a hardware has to fetch two consecutive memory words and rearrange them as to present single unaligned result (same goes for peripheral accesses).

In a hardware that does not support unaligned accesses (like MC68000 or some modes of ARM Cortex-M3 CPU), such access causes a trap or exception.

Other hardware might decide to mimic such access as being aligned and return just the whole word at the previous even byte address (so does the K1801VM1 CPU).

However, when the access is made to the "virtual" part of I/O space (as soon as registers are actually not peripherals or memory), the decoding hardware might as well do as in PDP-11/70: byte address determines register number, and no byte-wise accesses to the registers are possible.

Another consequence of such grouping is a small economy of I/O address space which is already quite crowded in PDP-11s!

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  • So if I understood this correctly: it all depends on what you're accessing. The cpu-registers: only words in that "packed address range". But others (like MMR0) can be accessed both at their low-order-byte, their high-order byte and as word. Right?
    – Folkert van Heusden
    Mar 30, 2022 at 13:41
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    Those registers mapped to I/O space might be 'virtual' -- i.e. accesses to them might early terminate inside the CPU without triggering a bus, and because of that they might have more relieved access rules. For any external bus or storage there's still the rule of odd/even bytes without unaligned word accesses.
    – lvd
    Mar 30, 2022 at 15:17
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    For most models, the "memory addresses" for registers are apparently accessible only by console. See this question. This likely implies console-specific decoding.
    – another-dave
    Apr 9, 2022 at 22:20

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