Can PDP-11 general registers be referenced by memory addresses?

Question

From time to time it is mentioned in RC that the PDP-11 general registers R0-R7 are accessible at addresses 177700 to 177717 (considered as 16 bit program addresses).

The mapping is as follows, again using 16-bit program addresses:

177717  User R6 (SP) 
177716  Supervisor R6 (SP) 
177715  R5 - General register set 1 
177714  R4 
177713  R3 
177712  R2 
177711  R1 
177710  RO 
177707  R7 (PC) 
177706  Kernel R6 (SP) 
177705  R5 - General register set 0 
177704  R4 
177703  R3 
177702  R2 
177701  R1 
177700  RO

Reference: Appendix A in the PDP-11/70 Processor Handbook.

Note the strange feature that there is a sequence of word-width registers whose addresses increase by 1.

Can PDP-11 general registers be referenced by these memory addresses on all models?

I intend to post my own answer to this, in order to establish a canonical instance of the answer.

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About PDP-11 addressing: the PDP-11 has a 16-bit virtual address, i.e., the address(es) in an instruction are 16 bits. The physical address space may be 16, 18, or 22 bits, depending on model. So you may see these addresses written as 1777xx, 7777xx, or 177777xx, depending on context. But they're always in the top 4K words of the particular address space.

For systems with a memory management unit: if the MMU is disabled, then virtual addresses 000000 to 157777 correspond directly through to physical space; 160000 to 167777 are mapped to the top of physical space (the 'I/O page'). If the MMU is enabled, then the mapping is up to software, but it is conventional to use the same I/O page mapping for privileged code.

To examine I/O page addresses from the PDP-11/70 console, the easiest approach is to set the address select rotary switch to CONS PHY, and set the 22-bit physical address on the switches.

Answer 1

Most PDP-11 models can use the addresses listed to examine the registers from the console (subject, of course, to the capabilities of the hardware: not all PDP-11s have two register sets, not all PDP-11s have three processor modes).

The exceptions for console access are the 11/23, 11/24 (both of which used the F-11 CPU), LSI-11, and all processors using the J-11 CPU. The registers on these systems cannot be accessed by memory address at all.

However, for most models, the general registers are accessible to the console but are not accessible to the CPU via memory addresses. Attempted access will incur a bus timeout. This applies to 11/04, 11/15, 11/20, 11/34, 11/35, 11/40, 11/44, 11/45, 11/60, 11/70.

The models for which both the console and the CPU can access the registers via memory address are only the 11/05 and 11/10.

Source: PDP-11/94-E System User and Maintenance Guide, Appendix D.3, Table D-2. The 11/94-E is one of those systems using the J-11.