x86 memory alignment

Question

For the 8086, unaligned word loads (first byte at an odd address) require two memory accesses, but an aligned word (first byte at an even address) can be loaded in one. This is excellently explained by answers over at Electronics Stack Exchange: ‘Accessing odd address memory locations in 8086’.

How has alignment changed with later processors, particularly with the introduction of 80386 and x86-64? Does byte/word/double word/quad word alignment versus misalignment have any latency differences on later x86 processors? A lesser question but still of interest, does the bus high enable (BHE) pin still exist on modern x86?

Answer 1

It depends on the CPU.

A 386SX has a 16-bit bus, so loading a double word would need to access only two or up to three memory addresses to load a double word. It would have a BHE or equivalent to load only high byte or full memory word.

A 386DX has a 32-bit bus, so loading a double word would need to access only one or up to two memory addresses. It would not have a single BHE equivalent, because each memory address is four bytes, so it would have four Byte Enable lines to load a byte, a word, or a double word from the 32-bit bus, or a part of it if a word or double word is loaded from un-aligned address.

A modern X86-64 would not be retro any more.

Answer 2

For the 8086, unaligned (first byte is odd) word loads require two instructions, but an aligned (first byte is even) word can be loaded in one instruction.

Sorry, but that's wrong. It will be one instruction in either case, as loading a 16 bit value is the same single instruction, no matter if it's pulled from an even or odd address.

What reading a 16 bit word from an odd byte address in a 16 bit wide memory system requires is that this single instruction has to do two byte fetches. Two memory cycles (each two clock cycles) will get issued.

How has alignment changed with later processors, particularly with the introduction of 80386 and x86-64?

Sorry, but beside that asking for today's CPUs isn't on topic, it's as well a way too wide area - Intel alone produced CPUs bearing any thinkable combination of factors, plus there were/are more then two dozen other x86 manufacturers as well.

Does byte/word/double word/quad word alignment versus misalignment have any latency differences on later x86 processors?

This depends on a multitude of factors (which is rather a generic CS question, isn't it?)

• access type
• memory width/used CPU bus width used
• alignment in relation to memory width
• cache line size
• alignment in relation to cache line size
• All of the above multiplied by cache levels.

So pick your favourite CPU and try again :))

A lesser question but still of interest, does the bus high enable (BHE) pin still exist on modern x86?

Again, asking about modern is by default off-topic - and as well, any combination of bus size signals you may think of have been made. So better check the data sheet of either CPU you're interested in.