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For the 8086, unaligned word loads (first byte at an odd address) require two memory accesses, but an aligned word (first byte at an even address) can be loaded in one. This is excellently explained by answers over at Electronics Stack Exchange: ‘Accessing odd address memory locations in 8086’.

How has alignment changed with later processors, particularly with the introduction of 80386 and x86-64? Does byte/word/double word/quad word alignment versus misalignment have any latency differences on later x86 processors? A lesser question but still of interest, does the bus high enable (BHE) pin still exist on modern x86?

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    This is very much CPU-specific, but the alignment penalty generally comes from having to do extra memory accesses. On modern x86-64, RAM is read in entire cache lines (64 bytes, usually) and so as long as the access doesn't straddle a cache line boundary, there is usually no penalty. But that's modern CPUs and this is RCSE. Do you have any particular retro x86 CPUs in mind?
    – pndc
    Apr 20 at 20:39
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    Are you confusing 'instruction' with 'memory access'? In many CPUs, a single unaligned load/store results in two read/writes to memory. Apr 20 at 23:33
  • Yes, this ought to be clarified before people start rushing FGITW answers. Apr 21 at 4:55
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    Also keep in mind that x86 is the odd CPU when it comes to alignment: Other CPUs (also "later" than 8086) have much stricter alignment requirements, and just don't allow unaligned memory access, so it's up to the compiler to properly align everything, or generate code that deals with unaligned access.
    – dirkt
    Apr 21 at 5:08
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    Also related re: evolution of x86 bus widths is the evolution of atomicity guarantees: Why is integer assignment on a naturally aligned variable atomic on x86? - P5 Pentium (still purely a 32-bit CPU) and later guarantee that 64-bit aligned load or store are atomic. On P5, that's only doable via x87 FPU fild or similar, but that's still better than lock cmpxchg8b. Apr 22 at 7:49

2 Answers 2

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It depends on the CPU.

A 386SX has a 16-bit bus, so loading a double word would need to access only two or up to three memory addresses to load a double word. It would have a BHE or equivalent to load only high byte or full memory word.

A 386DX has a 32-bit bus, so loading a double word would need to access only one or up to two memory addresses. It would not have a single BHE equivalent, because each memory address is four bytes, so it would have four Byte Enable lines to load a byte, a word, or a double word from the 32-bit bus, or a part of it if a word or double word is loaded from un-aligned address.

A modern X86-64 would not be retro any more.

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For the 8086, unaligned (first byte is odd) word loads require two instructions, but an aligned (first byte is even) word can be loaded in one instruction.

Sorry, but that's wrong. It will be one instruction in either case, as loading a 16 bit value is the same single instruction, no matter if it's pulled from an even or odd address.

What reading a 16 bit word from an odd byte address in a 16 bit wide memory system requires is that this single instruction has to do two byte fetches. Two memory cycles (each two clock cycles) will get issued.

How has alignment changed with later processors, particularly with the introduction of 80386 and x86-64?

Sorry, but beside that asking for today's CPUs isn't on topic, it's as well a way too wide area - Intel alone produced CPUs bearing any thinkable combination of factors, plus there were/are more then two dozen other x86 manufacturers as well.

Does byte/word/double word/quad word alignment versus misalignment have any latency differences on later x86 processors?

This depends on a multitude of factors (which is rather a generic CS question, isn't it?)

  • access type
  • memory width/used CPU bus width used
  • alignment in relation to memory width
  • cache line size
  • alignment in relation to cache line size
  • All of the above multiplied by cache levels.

So pick your favourite CPU and try again :))

A lesser question but still of interest, does the bus high enable (BHE) pin still exist on modern x86?

Again, asking about modern is by default off-topic - and as well, any combination of bus size signals you may think of have been made. So better check the data sheet of either CPU you're interested in.

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  • AMD64 exist since 20 years, not exactly today. Apr 21 at 11:26
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    @12431234123412341234123 See en.wikipedia.org/wiki/List_of_x86_manufacturers . In particular, Cyrix, Transmeta, NEC, and TI.
    – Sneftel
    Apr 21 at 12:17
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    @12431234123412341234123 RC.SE is about stuff no longer used. AMD64 is still used today. Well, except for the fact, thet AMD64 is not a bus implementation, which the question is about, but an instruction set. Instruction sets doe (usually) not define how physical access is done, just logical.
    – Raffzahn
    Apr 21 at 14:41
  • @12431234123412341234123: There have been various x86 clone vendors over the years (like Cyrix and Transmeta being some of the later 32-bit examples), but far fewer x86-64 vendors. Just AMD, then Intel, and Via. And apparently Zhaoxin continuing Via's design. Building an x86-64 that can meaningfully compete with modern OoO exec CPUs is a much bigger challenge then it used to be. (And probably patent-encumbered if Intel managed to patent anything about decoding x86 to uops in their P6 design that came out in ~1995, so their patent-sharing agreement with AMD probably keeps the market closed.) Apr 21 at 14:50
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    "Two memory cycles (each two clock cycles) will get issued." That's true for the 80286 and 80386. On the 8086, a memory cycle takes four clock cycles, so a misaligned 16-bit access requires 8 clocks. Apr 24 at 20:48

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