I'm trying to figure out why emulation of the ASH instruction by my emulator is marked as faulty. I use the XXDP+ "EKBBF0" test to verify its cpu emulation.

If I look at the source-code of EKBBF0, then I see:

3468 006500 072100    ASH R0,R1   ; EXECUTE INSTRUCTION UNDER TEST

...as if 00 means register R0 and 1 means register R1 (R1 being the register to be shifted).

(3468 is the line number, 006500 the addres of the instruction and 072100 the opcode)

In the "PDP-11/70 Handbook 1977/'78" on the other hand,

ASH / Shift Arithmetically / 072RSS

The contents of the register are shifted right or left
the number of times specified by the source op-
erand. The shift count is taken as the low order 6
bits of the source operand. This number ranges
from -32 to +31. Negative is a right shift and
positive is a left shift.

This description makes me think the lower 6 bits are not an "addressing mode + register number" but a signed value instead.

What is the right interpretation?

  • 1
    I think the fact that the number of bits used to select an addressing mode matches the number of bits used by the shift amount is coincidental. There are many situations where it may be useful to have an operation "If N is less than 16, shift X left by N bits, and if N is 16, load X with zero". In situations where N might be 16, such an operation is often more useful than "Shift X left by (N & 15) bits", and thus it's worthwhile to have hardware look at bit 4. Looking at additional bits would add cost without much benefit.
    – supercat
    Jun 3, 2022 at 16:30
  • There's probably some commonality (in the implementation) between ASH and the double-length ASHC, which of course needs to be able to shift by 31 bits.
    – dave
    Jun 3, 2022 at 17:07

1 Answer 1


I think you're confused by the meaning of "source operand".

The 6-bit mode-and-register field in the instruction is not the operand, it specifies the operand.

So, in ASH R0,R1, the shift is taken from the low bits of R0.

Likewise for all other addressing modes; ASH #3,R0 is a 3-bit left shift, where there is a second word in the instruction stream, containing the value 3.

Note that the source operand comes first in MACRO-11, despite the fields in the instruction being "destination register, source operand". That confused me at first (it's been a long while since I wrote any PDP-11 code...).

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