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Intel’s 8085 used bus multiplexing to stuff more functionality into 40 pins than would otherwise be possible. One of those pins, ALE, signals when the AD0…7 pins are outputting the low byte of the address which is about to be read/written. This saves seven pins (eight dedicated address pins, minus the ALE pin).

However, this means the 8085 cannot be used for any purpose without using an external latch (either built-in to other chips, like the 8185, 8355, 8755, or with a separate 74xx latch).

Other microprocessors I am familiar with, such as the WDC 65816 and the RCA 1802, latch the highest byte instead. To me, latching the high byte makes more sense: you can ignore the high byte if your application only needs 8 bits (or 16 bits, for the 65816) of address space. So you could have up to 256 bytes of ROM and some I/O peripherals, and still make a very useful computer, without using any additional components. The high byte is an upgrade you can “pay” for only when you need it.

Why did Intel choose to go the other way?

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    The 8085 memory layout for both data and instructions uses little-endian byte ordering. If any data is passed around sequentially on an internal 8-bit bus, it might follow the same little-endian ordering, low order bits first. Since the indirect address mode used the same registers (or register pair) for both data and memory addresses, the bytes would be passed around on a byte sequential bus low order first. If to address pins, this requires the low address byte to be latched. Why waste transistors and metal layer wiring area on a byte swapping bus? That costs!
    – hotpaw2
    Commented Jun 16, 2022 at 3:25
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    @hotpaw2 Maybe, then again, the 8085 was designed at a time when an additional on chip latch or buffer wan't as big of a deal anymore. The extended resources could rather be used to create a bus fitting the external needs, without following internal constrains.
    – Raffzahn
    Commented Jun 16, 2022 at 4:23
  • I've read in the biography of Frederico Faggin, that Intel had an obsession at that time of keeping the packaging of the chips as small as possible. That's why 4004 and 8008 have so few pins and multiplexed a lot of pins. I suppose that this smallest package size mentality still somehow was going on at Intel when they designed 8080, 8085and 8086. Commented Jun 16, 2022 at 6:39

1 Answer 1

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The reason is already within your question when looking at

... like the 8185, 8355, 8755, ...

and

So you could have up to 256 bytes of ROM and some I/O peripherals, and still make a very useful computer, without using any additional components.

while remembering that the 8085 is especially designed to enable very low chip count/embedded systems.

Or as Intel describes it on p.1-9 of the 1979 MCS-80/85 Family User's Manual:

The MCS-85 was designed to minimize the
amount of components required for most
systems. Intel designed several new peripheral
components that combine memory, I/O and
timer functions to fulfill this requirement. These
new peripheral devices directly interface to the
multiplexed MCS-85 bus structure and provide
new levels in system integration for today's
designer

By multiplexing the low 8 address bits with data, a chip like 8155 can provide 256 bytes of RAM and three I/O ports (*1) in a single 40 pin package. If data would have be multiplexed on the high address, only two would have been possible. Similar the 8355/8755 can support two 8 bit ports in addition to a 2 KiB (EP)ROM.

A basic system RAM, (EP)ROM and I/O can be done in just three 40 pin DIP packages:

enter image description here

(Figure 1-1 from p.1-10 of the 1979 MCS-80/85 Family User's Manual)

That's

  • 2048 Bytes ROM
  • 256 Bytes RAM
  • One 14 Bit Timer
  • 38 I/O Lines
  • Two Serial Lines

All without any need for any additional decoding or latching. That's a pin density not far from single chip controllers, but with a full figured CPU bus.

By adding a 8156 RAM and I/O can be almost doubled

  • 256 Bytes RAM
  • One 14 Bit Timer
  • Two 8 Bit Ports
  • One 6 Bit Port

(Similar with another 8755 for EPROM and more I/O)

Still all without the need for decoding, latching or whatsoever, as the chips are intended to work as system.


Bottom line: It's all about delivering a high integrated, low pincount system, not just a CPU.


The whole idea was carried over to the 8088 (*2) allowing really nice minimal "16" Bit systems:

enter image description here

(Figure 11b from p.6-26 of the 1979 MCS-80/85 Family User's Manual, titled "8088 Five Chip System Configuration")

The 8185 is a dedicated 1 KiB RAM in an 18 pin DIP. Again with two CS lines, like the 8755, allowing to add more still without further decoding.

The 8185 didn't become very popular outside the embedded world and even there it served only a very narrow band of use cases. Anyone needing more RAM would prefer standard chips for their size and price. Especially as larger applications already had to add a latch and dedicated decoding to support (EP)ROMs for their increased code needs.


*1 - Plus timers.

*2 - After all the 8086 was only a stop gap measure to keep customers that outgrew the 8085 address space, and the 8088 was a later added version capable to integrate in an existing 8085 design with minimal changes - I've seen some where the 8088 was integrated via a daughter board plugged into an 8085 system.

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    Oh that is a great point, it’s about minimizing pins on all the components, not just the CPU. The 8185 shows this extreme simplicity: 1024 bytes of static RAM in a DIP-18. Commented Jun 16, 2022 at 3:33

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