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While attempting to write a PDP-11/34 emulator, I noticed that there's a bit called "maintenance" in the MMR0 (SSR0) register (the 8th).

What does it do?

In the manual I read:

Maintenance/Destination Mode, Bit 8 - Bit 8 specifies that only destination mode references will be relocated using Memory Management. This mode is only used for maintenance purposes.

Does this mean that if I have the following instruction:

MOV (R0), (R1)

that it only performs virtual -> physical addressing for (R1) and not for (R0)? That would hardly make sense I think?

As the diagnostics (FKTH from XXDP+) use this mode, I would like to emulate it as well.

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  • 3
    From Faint Memory: Direct loaded programs can use this to access (copy) data from their boot location (code/data) - which is always within the first 64 KiB - to any destination within the segmented address space without having to manipulate the segmentation setup to reach the data. It's like having an additional private address space outside and in addition to the regular 64(+64) KiB. I remember this being used with utilities loaded via paper tape. Also, it was available on more machines, not just the 11/34. Not available on single chip though.
    – Raffzahn
    Jun 16, 2022 at 13:05
  • It's a maintenance, i.e., diagnostic provision. It makes sense if your object is to determine if memory management is functioning correctly - you can test "one thing at a time".
    – another-dave
    Jun 19, 2022 at 18:48

1 Answer 1

Reset to default
8
+350

The CPU Maintenance manual gives a bit of additional information:

Maintenance/Destination Mode

Bit 8 specifies maintenance use of the memory management unit. It is used for diagnostic purposes. For the instructions used in the initial diagnostic program, bit 8 is set so that only the final destination reference is relocated. It is useful to prove the capability of relocating addresses, in destination mode only.

So you can have a test program run with basically memory management disabled (so in particular instruction and data fetches won't be affected by a damaged MMU), and then write something to memory and have MMU relocation effective only for the final write of that step. Then you can read back the value from where it should be, but without MMU relocation, and in this way you can test whether MMU works correctly, under a variety of MMU settings.

It should be easy enough to implement in an emulator, as you have to make MMU conditional anyway. Just separate the MMU relocation for the final write from all other MMU relocations.

Ok, but how does it work? Which commands are different in what way?

From the description, any commands that write to memory, and only the final write access is relocated in maintenance mode.

I did not trace out the actual mechanism in detail, but the microcode has a ENAB MAINT bit (same manual, page 4-76). I would expect this bit to be set in the microcode ops that do the final write. I'd also expect this line to be processed together with the MAINTENANCE MODE and ENABLE MANAGEMENT bits in Status Register 0 to either bypass MMU relocation or perform the relocation.

That should be easy enough to verify in the microcode listings and the schematics, but that needs a bit of time investment, in particular as I couldn't find the manual with the explanations for the microcode for the 11/34, so I'd have to piece together the whole microcode first.

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  • Ok, but how does it work? Which commands are different in what way?
    – Folkert van Heusden
    Jun 19, 2022 at 12:49
  • I think there's an important point made in this answer - that instruction fetches are not relocated. and therefore you can execute code to test the MMU. If the code were also relocated, you'd be a on shaky ground as soon as you enabled memory mgmt. The diagnostics are here for inspection.
    – another-dave
    Jun 20, 2022 at 21:01
  • FWIW, I'd expect one of the operands of (for example) CMP to be relocated even though there is no write to memory. One of the operands is still the 'destination'. Per the usual handbook, the 1-operand instructions have a destination, the 2-operand instructions have a source and a destination. The EIS instructions seem to vary as to whether they have a source or a destination.
    – another-dave
    Jun 20, 2022 at 21:10
  • @another-dave As microcode for read and write to destinations is probably different, CMP is definitely something one would need to check the microcode for...
    – dirkt
    Jun 21, 2022 at 9:15

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