According to this preliminary datasheet and what appears to be a later CSG data sheet from some data handbook, the 6522 VIA assigns to registers 0 through 4, DR (data register) B, DR A, DDR (data direction register) B and DDR A.

This is swapped around from the arrangement in the original Motorola 6820 and 6821, and the MOS 6520 clone of the 6821, which ordered them as DR/DDR A, DR/DDR B. (They were multiplexed; a bit in the control register chose whether you were using the DRs or the DDRs.) The later MOS 6526 CIA also used this original ordering: DR A, DR B, DDR A, DDR B.

Is that preliminary data sheet correct, and the registers really are swapped around in the 6522, and swapped back in the 6526?

Bonus points if you can tell me why they did this.

  • Playing moving target is one thing, but doing so when the very premise of the question, the sequence of registers, shows to be wrong is hilarious.
    – Raffzahn
    Jun 23, 2022 at 10:38
  • @Raffzahn I assume you're talking about my edit to correct the question to more clearly ask what I wanted to ask. I'm sorry you find that "hilarious," and I'm sorry you don't understand how StackExchange works.
    – cjs
    Jun 23, 2022 at 14:46
  • Exactly that edit. To me it is quite hilarious when one changes the very premise of a question over admitting having misread the cited documents in the first place. But you may be right in that I do not understand the workings of SE the same way you seem to do. For me it's about a humble quest for truth, not the ego game to be played at all cost, no matter how damaging it may be to the site.
    – Raffzahn
    Jun 23, 2022 at 20:43
  • @Raffzahn I did not change the premise of the question; you misread it and focused on something entirely unimportant. That my clarification made the question look entirely different to you simply shows how badly you misread it. As for "humble quest for truth," that is about as far as one can get from the attitude you're taking in your one-upmanship games you're playing in comments like the ones you've made above.
    – cjs
    Jun 24, 2022 at 1:26

1 Answer 1



The 6520/21 does not swap the ports, but differs from all other MOS interface chips, as Data and Direction registers share the same addresses. There is no flipping of sequence or flipping back between 6520 and 6522. The 6520/21 is an outlier to the 6500 family due being a direct functional clone of Motorola's 6820 (note the E signal on pin 25 (*1)).


I just browsed a bunch of paper sheets (Rockwell, MOS, Commodore, Synertek). All found information lists them as

0000 - ORB/IRB - Output/Intput Register B
0001 - ORA/IRA - Output/Intput Register A
0010 - DDRB    - Data Direction Register B
0011 - DDRA    - Data Direction Register  and books


For the 6520 (as well as the 6521) it's noteworthy that these registers are not organized as with the 6522 (*2). Where the 6522 features 4 address (register select) lines for its 15 registers, the 6520 features only 2 (RS1/RS0), but has to operate 6 registers. Thus the corresponding data (ORx/IRx) and direction registers (DDRx) share the same address. 00 for port A and 01 for port B.

Data registers and direction registers do not have separate addresses as the question implies

The other two addresses are used to access either control register (CRx).

Which register, Data or Direction, responds to address 0x is defined by bit 2 (2^2, value 4) of the corresponding control register (CRx). When set (=1) the data register (IRx/ORx) are accessible, when reset (=0), the direction registers are accessible. The Bit is cleared after Reset.

00  0   - DDRA    - Data Direction Register A
00  1   - ORA/IRA - Output/Intput Register A
01  0   - DDRB    - Data Direction Register B
01  1   - ORB/IRB - Output/Intput Register B
10  x   - CRA     - Control Register A
11  x   - CRB     - Control Register B

The workings are well described in Section 1.5 (p.) of the 1976 Hardware Manual p.50ff (likewise all corresponding manuals of second source manufacturers).

For all practical use this 'hiding' of the direction registers makes sense, as they are only required during interface initialization, so an additional effort for access isn't a burden, while halving the needed address space (4 instead of 8) is a great gain - especially in embedded systems where one might want to pack many interfaces into the Zero Page for quick access.

6526 /653x

The 6526 has, like the 6522 and all other except 6520/21, 4 address lines thus enough address space to have all registers present at all time. As noted the sequence of A and B is turned:

0000 - ORA/IRA - Output/Intput Register A
0001 - ORB/IRB - Output/Intput Register B
0010 - DDRA    - Data Direction Register A
0011 - DDRB    - Data Direction Register B

Same goes for all 653x chips. The 6523/25 TPIs reordered them again as 3 data registers followed by three direction registers (and 2 control registers of the 6525) accessible by 3 address lines.


As to why this is can only be speculated.

Going by introduction, manual/data sheet publication and availability it's clear that the 6530 was done before the 6522, together with the 6520, thus the sequence of development is most likely 6520, 6530, 6522, 6526. All happened before MOS being bought by Commodore and several years before the 6526 was designed.

The fact that all early (1966/77) chips hint that there was, unlike the question implies (*2), no intention in keeping the same sequence.

Keeping them in the same order does not add much hardware or software wise. Not with the somewhat overlapping 6530/6522 and even less with all later. As soon as a symbolic assembler is used, it comes down to using the right include file - which had to be specific to each chip anyway.

*1 - Later redefined as Phi0 in Commodore's data sheet - although the timing diagram still reads 'Enable'. WDC's 2010 65C21 data sheet redefines it as Phi2, while still having the same function as Motorola's E(nable) of validating any CPU access.

*2 - The idea that keeping some sequence is to be kept for 'compatibility' seems to be based on a mindset not present back then. Heck, even today most embedded designers do not really care for sequence of I/O registers. Not in Assembler and even less in C.

*2 - Assumed as "DR A, DR B, DDR A and DDR B" something never shown in any sheet (it has been redacted as reaction to this answer).

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