What happens if a segment register plus offset overflows the 20-bit address space of the 8086? I assume it wraps around to 00000h, but want to confirm. For example, say DS is F001h and the offset is FFF0h. Would I then be reading 00000h?

1 Answer 1


On an 8086, yes, the address space wraps around. Thus a segment address of F001h and an offset of FFF0h, producing an address of F0010h + FFF0h = 100000h, wraps around to 00000h.

The 8088, 8086, 80188 and 80186 only have 20 address lines, so bits beyond that don’t correspond to anything and aren’t seen by the bus. Thus asking for 100000h in the CPU results in an address of 00000h on the bus, the top bit is lost.

On systems built around later CPUs, the behaviour depends on the A20 gate¹ (if there is one), which allows the 21st address line (A20) to be enabled or disabled. If the line is disabled, the behaviour in real mode ends up being the same as on the 8086. If it is enabled, addresses don’t “wrap around”; this can be used to provide access, in real mode, to the first few kilobytes of the second megabyte, known as the high memory area. A number of products could use this memory to reduce their footprint in conventional memory; perhaps most famously, DR DOS 5.0 and MS-DOS 5.0 and later could use it, which produced considerable memory savings (and the famous “Packed file corrupt” error message with some programs).

OS/2 Museum has a number of articles exploring this address wrap-around and the A20 gates: notably Who needs the address wraparound, anyway?, The A20-Gate: It Wasn’t WordStar, EXEPACK and the A20-Gate, and The A20-Gate Fallout.

¹ The 80286 and 80386 don’t provide control over their address lines; when IBM designed the PC AT, they added external hardware to control A20 so that backward compatibility with the original PC could be preserved when running DOS. The A20 gate was initially handled by the keyboard controller, and later by motherboard chipsets. Intel added A20 control to their CPUs starting with the 80486; this still required help from the chipset. CPUs from the last decade (Haswell and later) no longer have an A20 gate.

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    @Raffzahn calls this “address wrap” in footnote 10 on retrocomputing.stackexchange.com/a/6824/11579 Commented Jun 23, 2022 at 17:17
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    OS/2 Museum has a detailed post on the A20 gate, INT 30h, and the sordid history of address wraparound in the name of CP/M compatibility: os2museum.com/wp/who-needs-the-address-wraparound-anyway
    – Jim Nelson
    Commented Jun 23, 2022 at 17:50
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    @JimNelson "the sordid history", indeed! :) Commented Jun 23, 2022 at 20:49
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    Would there have been any particular downside to designing the IBM AT so that addresses whose top two bits were clear would have the next two bits forced to 10, and then wiring the board so memory would start at physical address $20000, so that memory from $20000 to $29FFF would be mirrored at $0000-$09FFF and $10000-$19FFF, without having to flip any external latches? That would allow a protected mode OS to treat all of RAM as contiguous.
    – supercat
    Commented Jun 24, 2022 at 16:06
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    @supercat apart from losing 2MiB out of 16, I can’t think of any, as long as the mirroring applies to the bus everywhere and not just between the CPU and the bus (so that cards and the DMA controller have the same view of the bus as the CPU). Commented Jun 24, 2022 at 16:32

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