In UK secondary education, there's a model called the fetch-execute cycle, which describes how computers work. (See: Isaac CS; Bitesize GCSE, Higher; Teach CS.) As I understand it:

The processor has at least one general-purpose register, usable as a source for arithmetic operations, and a source or target for MOV operations, plus the following special-purpose registers:

  • Program counter (PC), holding the address of the next instruction to execute.
  • Status register (SR), holding:
    • Flags like overflow, carry, zero, negative (set on an ALU operation)
    • Whether particular interrupts are due to be raised
  • Accumulator, where the result of all ALU operations is stored.
  • Current instruction register (CIR).
  • Memory address register (MAR).
  • Memory buffer register (MBR) aka memory data register.

The registers are faster to access than main memory.

Execution can be divided into four three phases: fetch, decode and execute.

  • In the fetch phase, the instruction at the PC is fetched, and stored in the CIR. The PC is incremented before the next fetch.
  • In the decode stage, the "control unit" decodes the instruction from the CIR, and decides which parts of the processor should handle it.
  • In the execute stage, the sequence of register moves, memory accesses and ALU operations required to implement the instruction is executed.
  • If interrupt flags are set in the status register, the corresponding ISR (interrupt handler) is called. (It's unspecified how this happens; this phase of the execution model doesn't even get a name.)

There is an ALU that handles arithmetical, bitwise and comparison operations. Memory accesses involve three buses:

  • Data bus
  • Address bus
  • Control bus

The MAR and MBR are buffers for the address bus and data bus respectively: to perform a memory write, the MAR and MBR are set, then their contents are sent over their respective buses, along with a "please write to memory" signal on the control bus. To perform a memory read, the MAR is set, then sent over the address bus with a "please read from memory" on the control bus, and the signals from the data bus are written to the MBR.


  • A clock is involved in some part of the processor's execution.
  • The addressable memory is RAM (think core or MOSFET, not drum).
  • No pipelining1 or branch delay slots. An instruction is only executed once the previous instruction has finished.
  • RAM accesses may be cached.
  • There's a halt instruction.

Being an ignorant youth, I've never come across a computer processor I know to be designed this way. Searching for the terminology turned up the IBM 1620, which has an MBR/MDR distinction and – as far as I can tell – a similar memory bus design. (Unfortunately, it lacks the general-purpose registers, and the clearly-defined ALU.) I haven't found much else online; the search results are so swamped with teaching and revision resources that my usual approach fails.

Is there a computer that works like this? If not, which real-life machines are closest to this model?

1: Though you don't always lose marks for writing about pipelining.

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    Seems ordinary. Nothing in your description suggests that it is taught that the CIR, MBR, and MAR/MDR are visible to the ISA (i.e., can be named in instruction fields). Surely it makes sense that even today there are plenty of simple microcontrollers that access memory via a pair of buffers- one for the address bus and one for the data bus?
    – davidbak
    Commented Jul 3, 2022 at 1:51
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    @wizzwizz4 Many of the old CISC CPUs work this way. The 68020, for example, does. The execute cycle can be quite complex as it may execute a series of micro-instructions (certainly did so in the case of the 68020, for example.) I had a long long discussion with Dr. Hennessey about the 68020 vs the MIPS R2000, back around 1986 when I visited MIPs. The much earlier HP 21MX processor (1975 or so) allowed for creating new instructions by modifying the micro-instruction table (or modifying existing instructions that way.)
    – jonk
    Commented Jul 3, 2022 at 6:04
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    You may be interested in eater.net/8bit - a computer that implements that architecture. Commented Jul 3, 2022 at 9:35
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    Could you mention which processors you know and how they are different from the theoretical architecture you describe so why they don't fit with it? Because in general, that sounds like how early 8-bit CPUs work.
    – Justme
    Commented Jul 3, 2022 at 9:50
  • 4
    Just as an aside: this sounds like it hasn't changed much in the 25 years since I did my A-level computer science. i.e. as abstract models go, it's a pretty stable one. Note that in plenty of fields it's fine to have a characteristic example that nearly matches many real cases, but isn't a 100% match to any
    – Chris H
    Commented Jul 4, 2022 at 14:01

4 Answers 4


Is there a computer that works like this?

Erm, next to all?

FETCH-DECODE-EXECUTE is the basic execution cycle for each and every digital CPU. No matter if a Turing Machine or a Pentium. I suspect the question is rather about the abstract model used in those courses.

As a model-CPU it's simplified to the minimum viable number of elements, but with added items to simplify teaching as well. It forgoes of course any optimiztion that a real world CPU would have right away, like splitting MBR and MDR or only copy needed data items (instruction or address) into registers.

What may add confusion is that it includes registers that are usually not user visible like MAR or MBR. This is done so the internal operation, below the user model, are to be understood - but without going into real implementation (i.e. gates).

If not, which real-life machines are closest to this model?

As said, next to all (simple, synchronous) CPUs work like that.

Insert About Teaching vs. Engineering

The key word is 'like that', as what you see in this course is an idealized model tailored for teaching. This means there are not only parts left out or simplified, but also steps/workings/parts added to ease teaching. These elements may not be found in the same way, or at all, in real implementations.

Remember: The target of teaching is not to build something, but to make pupils understand the principles so the can (hopefully) later create their own design.

For example within the FETCH cycle video shows MBR and CIR being hosted in parallel but feed in sequence. This is a simplification, and in fact rather useless, especially in this combination. In a real world the data fetched get put right away into the CIR, as the sequencer knows it's fetching an instruction. In turn when a fetch is not about instruction, but data, the byte read will get moved direct into the MDR.

In fact, the very reason of having two names for the same register, MBR and MDR, shows already that there might be more to it in real life. It's perfect to 'answer' questions about buffering input, buffering output and holding data for operations. In reality MBR and MDR are often different registers

For teaching it's good to have a streamlined understanding of FETCH where data always going first into. It simplifies the understanding of that process by using always the same straight mechanic. Students may later discover that splitting the load up according to state will improve upon. But that's after understanding the simplified workings first.

A similar liberty includes that a single read fetches instruction and address(es) that go with them to later fit a single register (MDR/CIR) holding all of that (and the control unit later on again). This requires a structure long words and short addresses that hasn't been seen since very early machines (e.g. Zuse, Manchester Mark 1) - and even these machines did not store the same value multiple times. They had way better use for their slim number of logic elements than useless duplication.

Long story short: Teaching models are not only different from reality to reduce complexity, but as well expand to improve teaching (*1).

But let's take a real world CPU and look for where to find the elements. Hanson's diagram of the 6502 seems like a good start:

enter image description here

(Taken from the cleaned up version on his site)

The Registers of you school CPU are quite visible:

  • Program counter (PC):
    • Top Center in Light Blue
  • Status register (SR):
    • Bottom Left in Yellow
  • Accumulator:
    • Bottom Center in Green
  • ALU:
    • Center in Dark Blue
  • Current instruction register (CIR):
    • Top Left in Red
  • Memory address register (MAR):
    • Right Side in Brown
  • Memory buffer register (MBR):
    • TOP Center in Violett

Due being a strict 8 bit CPU, the 6502 needs to organize 16 bit parts (PC, MAR) as two 8 bit units. For the context of teaching they are one register. Likewise are secondary parts of registers, like the PC incrementer or the data hold registers for the ALU. These are marked here with thin lines.

Left unmarked are what the 6502 provides over such a minimal model:

  • Index Registers (X, Y; Lower Right side) and
  • Stack Pointer (S; Center)

The remaining boxes represent items that are usually left out of such models to reduce complexity.

  • Buffers and alike units to manage the busses. That are, together with the thin line marked secondary parts, what your teacher implies when saying things like 'Now the MBR is loaded into the ALU'.

  • Decode and Sequentialize of execution. The huge area to the left. It contains all logic to make the CPU tick, turn a Byte in the CIR into a sequence of steps to perform what that byte asks for.

Regarding the often cited 'Pipelining' of the 6502: There is none.

At least not in the sense of today's understanding of a pipeline with instructions going thru various stages of execution. It's more like a expedited read ahead (hence the name prefetch register) issued while the last execution cycle is still performed. This works as for many instructions (think of ADD), the last cycle is an internal to perform the operation, thus the bus is free to do a read ahead.

Removing this from the CPU wouldn't change much of the CPU, except making many instructions one clock slower. It's an optimisation that comes (almost) for free by arranging the data pathes the right way.

The same can be done with next to any other CPU. Including the most recent units - although, it might be hard to pin these basic elements within the ocean of optimization :))

*1 - And to support quick demise/answer of questions of students to advanced for that course.

  • 4
    @wizzwizz4 Why? Keep in mind, what you get presented is an idealized and simplified model, made to be understood easy. This does not only mean components are left out, but also steps/distinctions are made which are not needed in real life, or avoided right from the start without any additional cost. Like having the CIR being loaded from the MBR.
    – Raffzahn
    Commented Jul 3, 2022 at 10:50
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    I know it's a simplified, educational model. I'm quite a fan of it as an educational model. But more than one textbook acts like this is the One True Way that All Processors Work™, and I wanted to know whether any real-life processor actually worked the way it described. If the features we're calling "idealized and simplified" actually featured in a real-world machine, I shouldn't be annoyed by that.
    – wizzwizz4
    Commented Jul 3, 2022 at 10:57
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    @wizzwizz4 Well, that's exactly the point of that teaching-model of a CPU. A real world CPU hasn't many registers holding the same value, nor does the implementation hold the ones that exist in a single place. Already a simple like the Mark 1 holds instruction and address in different parts, despite being read in as one. But these are as mentioned simplifications. Look around, some of your fellow students may already have a hard time with this simplified beginners model, do you think they would get anything if that's split into smaller parts and the many ways they go?
    – Raffzahn
    Commented Jul 3, 2022 at 12:22
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    @wizzwizz4 There are very many ways to build a CPU - it has lots of small details and each time you look at a small detail you see that build it in several different ways. For example a CPU could be designed to continue sending the memory address from the register file, instead of transferring it to an MAR. It should not be expected that every single CPU operates exactly like the textbook - but it should be expected that simple CPUs operate approximately like the textbook and you could design one exactly like the textbook if you wanted. Commented Jul 4, 2022 at 13:02
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    @user253751 The OCR exams sometimes reference (their version of) the Little Man Computer, but afaik they expect you to have memorised the details. AQA allows broader answers than their teaching model, but it asks about their teaching model. I'm not sure about the others – but their past papers and mark schemes are available online, if you're curious.
    – wizzwizz4
    Commented Jul 4, 2022 at 13:15

Microchip PIC family of microcontrollers very closely resembles this model. They are widely used in embedded systems, you probably have several in your home. A block diagram of the architecture can be found in e.g. PIC16F84 datasheet and more information on the core in a separate document.

PIC16F84 block diagram

Detailed comparison

The processor has at least one general-purpose register, usable as a source for arithmetic operations, and a source or target for MOV operations

PICs have exactly one general-purpose register, the W register.

Program counter (PC), Status register (SR)


Accumulator, where the result of all ALU operations is stored.

Same as W register.

Current instruction register (CIR).


Memory address register (MAR).

Called FSR (file select register).

Memory buffer register (MBR) aka memory data register.

Same as W register.

The registers are faster to access than main memory.

Access to main RAM take a whole 4-clock instruction cycle, W register access happens in single clock cycle.

Execution can be divided into three phases: fetch, decode and execute.

PICs use four phases:

  1. Load instruction, increment PC, start next instruction fetch.
  2. Memory / operand read
  3. Execute ALU operations
  4. Memory / result write

There is an ALU that handles arithmetical, bitwise and comparison operations.


Memory accesses involve three buses: Data bus, Address bus, Control bus

Yes, though control signals haven't been marked on the block diagram.

A clock is involved in some part of the processor's execution.

Clock is divided into the four phases, non-branch instructions always take 4 clock cycles.

The addressable memory is RAM (think core or MOSFET, not drum).

There is addressable RAM and flash memory.

No pipelining1 or branch delay slots. An instruction is only executed once the previous instruction has finished.

The instruction fetches from flash are pipelined by a single stage (the fetch is started during previous instruction execution). There are no branch delay slots, but branches take 2 instruction cycles (8 clock cycles).

RAM accesses may be cached.

They are not.

There's a halt instruction.

There is a SLEEP instruction, which can be woken from by hardware pins.

  • Sounds very similar except for pipelined fetch, and possible implementation details of MBR/MAR. Your diagram is showing an IR, aka the Current Instruction Register from the UK machine model. Commented Jul 3, 2022 at 23:40
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    Since we're on Retrocomputing, that should be the General Instruments PIC, if you please :-) Commented Jul 5, 2022 at 11:34
  • @PeterCordes: One could view the PIC as using a pure non-pipelined fetch-decode-execute model within the CPU if one views the program store as simultaneously accepting an address for each cycle while it outputs the value fetched using the last address. If one does a GOTO, CALL, RETLW, or RETURN, or if one writes to the PCL, the code store will receive the address of the instruction following that operation, but hardware will suppress execution there. One thing I've sometimes thought would have been nice would have been an instruction which was similar to BTFSx, but which instead...
    – supercat
    Commented Jul 5, 2022 at 16:58
  • ...of replacing the following instruction with a NOP, would flip one bit of the opcode received from the code store--the one that selects between bsf/bcf, but that's getting outside the scope of this question.
    – supercat
    Commented Jul 5, 2022 at 17:04
  • @user_1818839: I find it interesting that some versions of the GI PIC used separate addresses for port latches and pin readback, but Microchip used shared addresses on many of their parts even when spare address space would have been available.
    – supercat
    Commented Jul 5, 2022 at 19:53

It is an extremely common approach for discrete CPUs (CPUs implemented with discrete logic elements, both with integrated circuits and previous technologies), and also in early single-chip CPUs.

Some examples (this is not a complete list):

  • DEC PDP-8. As you can see in the block diagram on page 2 of the User's Handbook, there is a memory address register (MAR), a memory buffer register (MBR), a program counter (PC), an instruction register, and an accumulator.

    There is no dedicated status register, but the "link" register which here is considered close to the accumulator would be part of the status register.

    The MAR and MBR registers are displayed on the front panel and can be changed via switches, in that way it is possible to trace the execution, and inspect and modify memory. (That also was a common approach).

    The execution phases (page 4) have an additional defer state (for indirect addressing) on top of fetch and execute, and decoding is implicit, there is no dedicated phase for it.

  • If you look at the block diagram of the 6502 CPU, you'll see two ABH and ABL latches (these correspond to MAR) and DOR/DL pair (corresponding to MBR). There is an Instruction Register (IR) and a PC (PCH and PCL) and a status register (P).

    Execution phases are a bit more complex, but the first phase is instruction fetch (which is actually in parallel with the last phase of the previous instruction), followed by a decode phase, followed by various execution phases.

(There are a lot more similar architectures)

So you can see variations of this were widespread, and from a teaching perspective, it makes sense to distill common elements and present those, as in your textbooks.

  • 2
    The PDP-8 doesn't seem to have an Instruction Register; AQA's 2017 A-Level exam, Paper 2, question 1(b) asks candidates to explain why "the instruction could not be processed directly from the MBR", so it seems that's an important part of the model. The 6502 has an instruction register, but also a pipeline. I know there are similar architectures (didn't know about the PDP-8, though), and this model is broadly how 8-bit microprocessors work, but it's the details that make it seem unfamiliar.
    – wizzwizz4
    Commented Jul 3, 2022 at 9:54
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    @wizzwizz4 the 6502's Predecode Register (CIR) is the pipeline. The whole pipelining trick is that the CIR is already loaded with a new value during the last clock of each instruction. It's a rather easy optmization, not shown in your Model as it only adds confusion.
    – Raffzahn
    Commented Jul 3, 2022 at 10:40
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    @wizzwizz4 Likewise Data read is in the 6502 not copied first into MBR and then into CIR, but directly into CIR. Keep in mind, what shown in this course is a simplified and idealized version of a CPU, a real one will work like it, but if course has to follow the principles of engineering, not the drawing of colour in Powerpoint.
    – Raffzahn
    Commented Jul 3, 2022 at 10:48

The old IBM1130 comes close. Here's the console, which displays much of the CPU state:

enter image description here





It has an extra ARITHMETIC FACTOR separate from the STORAGE BUFFER. I believe this is because core memory must be rewritten after each read, while multiply and divide involve multiple additions and subtractions with modified operands, so keeping these separate is handy.

The ACCUMULATOR EXTENSION supports multiple precision arithmetic, an added feature beyond your model.

  • It has a WAIT instruction, too. I'm not quite sure how ARITHMETIC FACTOR relates to STORAGE BUFFER (I thought I got it, then I looked at the diagram at the end of CPU Functional Characteristics) and I'm not sure whether the execution model matches, but this is a great find, thanks!
    – wizzwizz4
    Commented Jul 4, 2022 at 18:13
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    @wizzwizz4 Find? I used to program these ツ
    – John Doty
    Commented Jul 4, 2022 at 18:17
  • Ooh. How closely does the execution model match fetch, decode, execute, handle interrupts?
    – wizzwizz4
    Commented Jul 4, 2022 at 18:19
  • @wizzwizz4 That's how we thought about it as programmers. In hardware, there was a lot of finer-grained stuff going on. For example, parallel adder with serial carry, so it could take 15 clock cycles to compute a 16 bit sum, although it was usually fewer.
    – John Doty
    Commented Jul 4, 2022 at 18:25
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    The index registers have special treatment in the instruction representation… I'm inclined to say that this is a perfect (or near-perfect) match!
    – wizzwizz4
    Commented Jul 4, 2022 at 18:43

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