The processor has at least one general-purpose register, usable as a source for arithmetic operations, and a source or target for MOV operations, plus the following special-purpose registers:
- Program counter (PC), holding the address of the next instruction to execute.
- Status register (SR), holding:
- Flags like overflow, carry, zero, negative (set on an ALU operation)
- Whether particular interrupts are due to be raised
- Accumulator, where the result of all ALU operations is stored.
- Current instruction register (CIR).
- Memory address register (MAR).
- Memory buffer register (MBR) aka memory data register.
The registers are faster to access than main memory.
Execution can be divided into
four three phases: fetch, decode and execute.
- In the fetch phase, the instruction at the PC is fetched, and stored in the CIR. The PC is incremented before the next fetch.
- In the decode stage, the "control unit" decodes the instruction from the CIR, and decides which parts of the processor should handle it.
- In the execute stage, the sequence of register moves, memory accesses and ALU operations required to implement the instruction is executed.
- If interrupt flags are set in the status register, the corresponding ISR (interrupt handler) is called. (It's unspecified how this happens; this phase of the execution model doesn't even get a name.)
There is an ALU that handles arithmetical, bitwise and comparison operations. Memory accesses involve three buses:
- Data bus
- Address bus
- Control bus
The MAR and MBR are buffers for the address bus and data bus respectively: to perform a memory write, the MAR and MBR are set, then their contents are sent over their respective buses, along with a "please write to memory" signal on the control bus. To perform a memory read, the MAR is set, then sent over the address bus with a "please read from memory" on the control bus, and the signals from the data bus are written to the MBR.
- A clock is involved in some part of the processor's execution.
- The addressable memory is RAM (think core or MOSFET, not drum).
- No pipelining1 or branch delay slots. An instruction is only executed once the previous instruction has finished.
- RAM accesses may be cached.
- There's a halt instruction.
Being an ignorant youth, I've never come across a computer processor I know to be designed this way. Searching for the terminology turned up the IBM 1620, which has an MBR/MDR distinction and – as far as I can tell – a similar memory bus design. (Unfortunately, it lacks the general-purpose registers, and the clearly-defined ALU.) I haven't found much else online; the search results are so swamped with teaching and revision resources that my usual approach fails.
Is there a computer that works like this? If not, which real-life machines are closest to this model?
1: Though you don't always lose marks for writing about pipelining.