I came across an early mention of the ARM in New Scientist of June 18, 1987:


It has this statement:

They realised that many of the instructions they were planning to remove from their chip could be retained in the hardware if they created what they call “building bricks” in the chip’s design. These are short instructions that the software operating system can make into longer instructions.

Does anyone have any idea what this might be referring to? At first glance this seems to simply be describing the entire RISC concept, using "short" instructions. But one might also read this to be some sort of macro expansion, or even long-word. I'm not at all familiar with the early ARM sets, does anyone know if this is referring to anything special?

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    The wording is terrible, but I think they are probably referring to the microcode used in the ARM1. The original ARM instructions each used from 1 to 4 micro-coded instructions.
    – Brian H
    Commented Jul 10, 2022 at 15:34
  • @BrianH - But the microcode is presumably not exposed to software, so that doesn't fit the New Scientist claim.
    – dave
    Commented Jul 10, 2022 at 16:02
  • The Wikipedia ARM page says this: Another feature of the instruction set is the ability to fold shifts and rotates into the data processing (arithmetic, logical, and register-register move) instructions which seems like a reasonable candidate for an answer. Although it's unclear what version of the ISA is being discussed.
    – dave
    Commented Jul 10, 2022 at 16:10
  • @another-dave Also thought about that first, but it's way to limited to be called building blocks. I would rather go along with the obvious point about the instruction set being rather RISCy Especially when considering the way opcode and data fetch on the original ARM design is interleaved and how instruction can be chained/repurposed. Like using LM brings a transfer thruput quite close to DMA. Likewise does the feature of having each instruction conditioned create a 'toolset' of Building blocks. After all, many CISC operations are CISC because of decision making involved during execution.
    – Raffzahn
    Commented Jul 10, 2022 at 18:35
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    @BrianH, in retrospect I'm certain this is what they were referring to. I never imagined a RISC with microcode, given Codd's comments. I had never heard ARM1 used micro, and the first article I found on the topic notes it disappeared from subsequent designs. Commented Jul 11, 2022 at 13:13

1 Answer 1


Such short and rather terrible wording leaves a lot to be desired. In addition it's noteworthy that the article is most likely not well researched, as it states that only IBM has used RISC in an 'esoteric' workstation, while HP being still in research phase.

At the time of the article (June 1987), the PA-RISC-based HP3000 and HP9000 had already been in the market for more than a year (introduced Feb 1986). IBM's 1986 ROMP-based PC RT was not targeted at a mass market, but still a fine seller as an high end workstation (*1). Likewise the SPARC-based Sun 4/280 was introduced in early 1987 and became an instant seller. Last, but not least, 1987 saw several MIPS-based based work stations delivered (*2).

Long story short, the article seems rather intentionally geared toward ARM and tries hard to present it as special.

That aside, I would think it's for most part about the general RISC nature of the ARM, and the way in which several simple instructions can be chained to form complex ones. In particular, due the way of conditional execution without stalling.

A hint here is the comparison with the 80386 which has dedicated instructions for various register width or data item sizes. By being default 32 bit wide, ARM does skip many questions about 8, 16 or 32 bit handling. In addition larger items can be handled by chaining. Such as incrementing a 64 bit value by using two adds:

ADDS  R2,R2,#1
ADCS  R3,R3,#0

Similarly, all the variations of MOV of a 386 dependent on instruction and mode can be synthesized by combinations of LD*/MOV with optional shift factors.

Bottom line: It's a rather non-specific description pointing to RISC in general and ARM in particular.

*1 - And eventually used in 1988 for the first massive parallel RISC system with several hundred CPUs.

*2 - Given, all of them were designed for a high end market with top notch performance, while ARM targeted the low end of personal computing.

  • Raffzahn, the sentence beginning "Beside that the ARM is by default 32 bit" doesn't seem to make sense. The only parsing I could come up with was to replace "may" with "many" but that's still not that good. Perhaps you could revisit and edit?
    – paxdiablo
    Commented Jul 10, 2022 at 19:22
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    @paxdiablo thank you, it should have in fact read many. after all, much of the confusion (and bloat in instruction encoding) of the x86 lies in handling of different data types with (mostly) equal attention. I rephrased it as simper sentences - does that work?
    – Raffzahn
    Commented Jul 10, 2022 at 19:30
  • My ARM is rusty, but should the 64 bit addition be ADDS followed by ADDC (first ADD must set flags)?
    – abligh
    Commented Jul 11, 2022 at 6:22
  • @abligh yes, you'r right (also it's ADC). Mine is not only rusty, but I'm also gifted with big clumsy fingers :))
    – Raffzahn
    Commented Jul 11, 2022 at 8:21

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