Just for hobby and research purposes I design an XT compatible machine based on 8086, and now I have to come up with a wait state generator for IO devices that are slow and require additional time to do their own things. For this I need to understand when to activate/deactivate RDY inputs of 8284, which is going to synchronize it to the clock, and assert/deassert READY input of 8086. I am a bit confused, though, about how and when 8284 and 8086 sample their respective RDY and READY signals. 8086 datasheet states that:
RDY is sampled near the end of t2, t3, tW to determine if TW machine states are to be inserted.
So, if I want to insert a wait state, do I need to keep RDY inactive at the end of both t2 AND t3, or is it enough to have it deactivated only at the end of either t2 OR t3?
The 8086 Family User's Manual, confuses me even more, because when it comes to READY description, it does not mention t3 at all, and on page 4-10 it says:
Another question is about a wait state itself. Per Intel datasheet:
In the event that a “NOT READY” indication is given by the addressed device, “Wait” states (tW) are inserted between t3 and t4. Each inserted wait state is the same duration as a CLK cycle.
Of course, I tend to trust official documentation, but there are some other sources, like this one - http://ece-research.unm.edu/jimp/310/slides/8086_chipset.html which states that t3 becomes a wait state:
READY is sampled at the end of T2.
If low, T3 becomes a wait state.
And then just a few lines lower in the text there is another contradiction:
A wait state (TW) is an extra clock period inserted between T2 and T3 to lengthen the bus cycle.
So, what is a real wait state and when and where is it inserted into a bus cycle?