Just for hobby and research purposes I design an XT compatible machine based on 8086, and now I have to come up with a wait state generator for IO devices that are slow and require additional time to do their own things. For this I need to understand when to activate/deactivate RDY inputs of 8284, which is going to synchronize it to the clock, and assert/deassert READY input of 8086. I am a bit confused, though, about how and when 8284 and 8086 sample their respective RDY and READY signals. 8086 datasheet states that:

RDY is sampled near the end of t2, t3, tW to determine if TW machine states are to be inserted.

So, if I want to insert a wait state, do I need to keep RDY inactive at the end of both t2 AND t3, or is it enough to have it deactivated only at the end of either t2 OR t3?

The 8086 Family User's Manual, confuses me even more, because when it comes to READY description, it does not mention t3 at all, and on page 4-10 it says: 8086 READY description

Another question is about a wait state itself. Per Intel datasheet:

In the event that a “NOT READY” indication is given by the addressed device, “Wait” states (tW) are inserted between t3 and t4. Each inserted wait state is the same duration as a CLK cycle.

Of course, I tend to trust official documentation, but there are some other sources, like this one - http://ece-research.unm.edu/jimp/310/slides/8086_chipset.html which states that t3 becomes a wait state:

READY is sampled at the end of T2.
If low, T3 becomes a wait state.

And then just a few lines lower in the text there is another contradiction:

A wait state (TW) is an extra clock period inserted between T2 and T3 to lengthen the bus cycle.

So, what is a real wait state and when and where is it inserted into a bus cycle?

  • 2
    A tricky issue when dealing with 1980s data sheets is that they fail to make clear which inputs are fully double synchronized, and which ones could go metastable, with unpredictable consequences, if setup/hold times are violated. If the output of a circuit that latches a signal on a rising clock edge goes nowhere except to a circuit that latches the first latch's output on a falling clock edge, violations of the first latch setup/hold time would be very unlikely to make the second latch go metastable. If, however, the from the first latch went to multiple places, it's possible that...
    – supercat
    Jul 17, 2022 at 17:42
  • 2
    ...some downstream latches might perceive it has having been high on a cycle where others see it has having been low. This could, for example, result in a cycle where some address lines keep their values (as though a read wasn't yet completed) while others change (as though the read had been completed and it was necessary to output the next address). Unfortunately, 1980s documentation often seemed to suggest that the only possibilities would be for a signal to be recognized as occurring before a clock edge, or not, even device behavior could be an arbitrary mish-most of the two in bad cases.
    – supercat
    Jul 17, 2022 at 17:46

2 Answers 2


So, if I want to insert a wait state, do I need to keep RDY inactive at the end of both t2 AND t3, or is it enough to have deactivated only at the end of either t2 OR t3?

Let's dissect the text while peeking at the graphic:

  • Ready may be already pulled low during T2
  • When Ready is low before the end of T3 a wait cycle Tw will be inserted after T3
  • When Ready is low before the end of (a) Tw, another Tw is inserted
  • When Ready is high before the end of (a) Tw (or T3), T4 will be next
  • Ready input (from memory) is synchronized by the 8284 to Clock, making Ready output toward the CPU only change at the beginning of a clock cycle

Pulling Ready low during T2 ensures that it will be present during all of T3 after being synchronized by the 8284.

Of course, I tend to trust official documentation, but there are some other sources,

It's the net, there are many sources, this being a perfect example that multiple descriptions of the same item can be confusing, as different people may use different semantics. I.e., it's all about what to call it.

To circumvent these cliffs, it's important to understand what's happening:

  1. When Ready is pulled low during T3, The BIU waits
  2. A waiting BIU essentially repeated the actual cycle
  3. What to call repeated cycles is a up to everyone's own philosophy

There are three different ways to name these cycles:

  1. The first is T3 and all following are Tw
  2. The last cycle is T3, while all prior are Tw
  3. All are called T3.

Each of these is a valid view in its own and focuses on a certain aspect, but for practical purpose it is all the same:

  • T3 is repeated/extended until Ready is high again.

Intel chose to use #1, while the authors of the cited web-page go with #2.

Pick whichever you like, just keep in mind, it's all about a prolonged T3.


Adding to Raffzahn's detailed answer: The main takeaway is: Nothing actually happens during T3 or Tw. There is stuff happening around the time when T2 is over (like the processor outputting valid data on write cycles), and there is stuff happening when T4 starts (like the processor sampling data). So basically everything that happens during T3 is waiting, so I propose a fourth way of dealing with names: Just rename "T3" to "Tw".

For me, the bus protocol is easiest to understand as "1WS between T2 and T4 is required, but marketing insisted on not calling any required cycle a wait state, so we had to call one of the wait states T3".

When you deal with RDY at the 8284, you need to consider that synchronizing RDY with the clock to derive READY effectively delays RDY by one clock. To make sure you get a single extra cycle (i.e. a 5-clock bus cycle), you need to deassert RDY during T2, so the 8284 can inform the 8086 that the (first) T3/Tw is not going to be the only one. If you do not deassert RDY during T2, the 8086 won't recognize a demand for waitstates during T3, and perform a 4-clock bus cycle.

If you want more than one waitstate, you need to keep RDY deasserted. According to Intel's nomenclature, READY needs to be low not only during T3, but also during the Tw that has been added. Going back to RDY at the 8284: You do not only need to deassert RDY during T2, but also during T3.

So, if I want to insert a wait state, do I need to keep RDY inactive at the end of both t2 AND t3, or is it enough to have deactivated only at the end of either t2 OR t3?

I hope my explanation directly answers this question: You can not choose either t2 or t3, but deactivation during t2 is mandatory. If you want a single waitstate, have RDY deactivated at the end of t2 only. If you want two waitstates, have RDY deactivated at the ends of t2 and t3. If you want more waitstates, have RDY deactivated at the ends of t2, t3, and some number of tw cycles. If RDY goes active during a tw cycle, the 8284 keeps READY still inactive during this tw cycle and the 8086 will add another tw cycle, during which READY will be active to indicate that t4 is requested next.

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