Hitachi was a second source for the Motorola 6809 Micro Processor. The 6309 had many secret features. What advantages does the HD6309 have over the MC6809?
The basic improvements over the 6809: - 2 more 8bit accumulators; additional 8 & 16 bit registers - native and 6809 emulation modes - fewer execution cycles in native mode - improved instruction set - error trapping (illegal instruction & divide by zero) - roughly 10% speed increase in emulation mode/40% in native mode (both application dependant) - variants include 3Mhz parts.
Much more detailed information can be found in a memo written by Hirotsugu Kakugawa link.
Below are excepts from the link (this is NOT my writing, I'm reposting existing information):
The CPU 6309 by HITACHI has secret features which is not written in its manual. The purpose of this memo is to introduce them. The features was originally reported in a magazine, Oh!FM (1988 Apr.), which was written in Japanese. I did not tried all of the features reported in the article, but I report the features as far as I know.
HITACHI says in the manual of 6309 that 6309 is compatible with 6809, but some OS-9 hackers found that it has secret features.
It has following features: 1. More registers (additional two 8 bit accumulators, 8 bit register, and a 16 bit register), 2. Two modes (6809 emulation mode and native mode), 3. Reduced execution cycles in native mode, 4. More instructions (16 bit x 16 bit multiplication, 32 bit / 16 bit division, inter-registers operation, block transfer, bit manipulating operation which is compatible with 6801 has, etc) 5. Error trap by illegal instruction, zero division.
The 6309 has some additional registers that 6809 does not.
The E register, the F register These are 8 bit accumulators. Like the D register is a pair of the A register and the B register, these two registers can be used as a 16 bit accumulator. The pair of the E and the F registers is called the W register. In addition to that, pair of two 16 bit registers, the D register and the W register, can be used as a 32 bit accumulator called the Q register.
The V register This a 16 bit register can be used only by TFR, inter-register operation, etc. But even if the chip is reseted, contents of this register does not change. Some people may use this register to keep constant value (V for value).
The MD register This is a 8 bit register to keep the mode and status of the chip. The meaning of each bit is as follow.
Read value bit 7 --- 1 is set if zero division happen. bit 6 --- 1 is set if illegal instruction is fetched.
Write value bit 1 --- The mode for FIRQ interrupt. 0 -> the the action for FIRQ is the same as that of 6809. 1 -> the the action for FIRQ is the same as IRQ. bit 0 --- The execution mode of 6309. 0 -> the emulation mode. 1 -> the native mode.
(When the chip is reseted, all bits are 0.)
The 6309 has two modes, emulation mode and native mode, as described in the previous section. When the chip is reseted, the initial mode of 6309 is the emulation mode.
When the 6309 is in the emulation mode, the chip emulates the action of 6809. But we can use extended registers and extended operations in this mode. The 6309 executes instructions in the same cycles as 6809 does. When the 6309 is in the native mode, it executes instructions in less cycles. And when the chip is interrupted (IRQ, for example), it pushes extended registers (PC, U, Y, X, DP, W, D, CC, in this order). If you want to use the 6309, you must rewrite interrupt handling routine (for example, the entry of system call of OS9).
The Register Addressing Mode
To specify registers in TFR and EXG, the 6809 uses bit pattern of 4 bits. New registers of the 6309 are specified by bit patterns in TFR and EXG operations. In addition to that, the bit pattern is also used in instructions of inter-register operations. We call this bit pattern used to specify register "register addressing mode".
Bit patterns for new registres are as follows:
W -> 0110, V -> 0111, E -> 1110, F -> 1111.
NOTE: even if the 6309 is in a emulation mode, the action for TFR of 6309 is different from that of the 6809 if new register is specified in operand. Some hackers found this fact and they guessed that the 6309 has secret registers. At last, they found many features.
Inter-Register Operations Operations of 6809 are operations between register and immediate value or between register and memory. Therefore, we had to store value of register on memory if opetation between two registers is necessary. But the 6309 has inter-register operation. Following operations are provided: ADDR r0,r1 (ADD of two registers), ADCR r0,r1 (ADC of two registers), SUBR r0,r1 (SUB of two registers), SBCR r0,r1 (SBC of two registers), ANDR r0,r1 (AND of two registers), ORR r0,r1 (OR of two registers), EORR r0,r1 (EOR of two registers), CMPR r0,r1 (CMP of two registers). The register addressing mode is used to specify two registers. (I do not remember exactrlly but the result is stored in r0, the register of the first operand. Please try and find the behavior of these instructions.)
Block Transfer Block transfer instructions are provided such as Z80 has. The TFM instruction requires source address and destination address and block size as its argument. One or two 16 bit registers (X/Y/U/S) are used to specify source and destination addresses. Block size to be transfered is specified by the W register. Four style is provided: TFR r0+,r1+ (transfered in address is increasing order), TFR r0-,r1- (transfered in address is decreasing order), TFR r0+,r1 (poured into the same address, I/O port for instance), TFR r0,r1+ (read from the same address, I/O port for instance). I tried this instructions but I do not remember exactly. Operand registers are pointers of source/destination addresses (,maybe). Please try and find the behavior of these instructions.
Multiplication And Division The 6309 has MULD instruction which performs a 16bit x 16bit multipli- cation. We can use various addressing modes (immediate, direct, indexed, extend) The result is stored in the Q register. Division instructions are also provided. The 6309 has two division instructions: 16bit / 8bit, 32bit / 16bit divisions. Various addressing modes (immediate, direct, indexed, extend) can be used. (Note:I forget where its result is stored. I tried these instructions. I remember that modulo is also computed. The quotient and the modulo are stored D and W resp., maybe. I'm not sure, sorry.)
Bit Manipulation / Bit Transfer The 6309 provides AIM, OIM, EIM, TIM instructions which are compatible with instructions of the Hitachi 6301 CPU. Read the manual of the 6301 to understand thses instructions.
Instructions called BAND, BOR, BEOR, BIAND, BIOR, BIEOR, LDBT, STBT are provided. Behavior of thses instructions is that a logical operation is performed for n-th bit of a data in a memory (only direct mode is allowed) and m-th bit of a register, then the result is stored in the register. The format of the object is : $11, x, (post byte), (operand). The say that the post byte takes strange format. I do not understand these instructions. Sorry, please try.
To change modes ofthe 6309, we have to set the 0th bit of the MD register. To do this, the LDMD instruction is provided: LDMD #n (where #n is a immediate n bit data) When trap is caused, it is necessary to examine the reason of the trap. The BITMD instruction can be used for this purpose: BITMD #n (where #n is a immediate n bit data) The contents of the MD register and #n is ANDed, and changes the CC register (,maybe, I do not remember exactly). Once this instruction is executed, the 6th and the 7th bit of the MD register is CLEARED. Therefore, we can't examine the MD register.
Pushing and poping the W registers on/from stack: PSHSW (Push the W register on the system stack), PULSW (Pop the W register from the system stack), PSHUW (Push the W register on the user stack), PULUW (Pop the W register from the user stack).
It begins with a very thorough Leventhal-style instruction set reference, with everything 6309-specific clearly marked, then an in-depth article about the differences, then an opcode map, then a chart of undefined opcode behavior.