# Why are computer bus sizes integer multiples of the size of a byte, and when was that standardized? [closed]

Memory is organized in powers of two: 8 bits to a byte, then 16 bits to a short, 32 bits and so on. Some early computers did not necessarily have powers of two as their basic memory unit. When did it become standard to use only powers of two, and why? To me it doesn't make a ton of sense. For instance, if I have a 16-bit computer, a 32-bit computer would represent a huge difference in the size of everything. A 20-bit computer or something would be a more incremental increase.

• And there were computers that used 20-bit words. Are you asking about register size, bus width, what? Sep 6, 2022 at 18:20
• I don't have anything worth making into an answer, but I suspect it shares its origins with the hardware design decisions that result in CPUs having alignment requirements. CPU design has always been about finding the simplest circuits that meet a set of criteria. Sep 6, 2022 at 18:23
• This is pure speculation, but I suspect the market decided. When 8 bit CPUs became cheap and plentiful, adoption rates grew, increasing demand. I suspect RAM manufacturers went along for the ride, tooling up and making 8 bit rams because they were in demand. When 16 bit and 32 bit came along, the same process repeated itself. The market wants what the market wants. Sep 6, 2022 at 18:46
• It is very unclear what you are asking. For example a 68000 has 32-bit registers, a 16-bit data bus and 24-bit address bus. And original Pentium is a 32-bit CPU with 32-bit address bus, yet the data bus is 64-bit. Sep 6, 2022 at 21:45
• The title of the question is really confusing. To me, it sounds like you're asking about why each bit represents 2^x instead of 2*x, e.g. why `101` = 1(2^2) + 0(2^1) + 1(2^0) and not something based on multiplication. And the question body is very confusing to me as well. Sep 7, 2022 at 10:07

Address ranges come in powers of 2 because n address lines can select up to 2n addresses. For example, a memory chip with 11 address lines can select up to 211 = 2048 possible addresses. It is certainly possible to create a memory chip that uses less than the number of possible addresses (e.g. 2000 bytes instead of 2048), but such a chip would not be as commercially successful as one that uses the entire available address space.

(Note that most memory chips with a byte-wide data bus actually had an odd number of address lines: 211 = 2048 bytes, 213 = 8192 bytes, 215 = 32768 bytes, and so on. This is because such sizes require a perfect square number of memory bits, so the chip can be fabricated on a square die instead of a rectangular die.)

Data buses come in powers of 2 because microprocessor word sizes have been powers of 2. My previous answers here and here explain why. Briefly, the first microprocessors had 4 or 8 bit word sizes (both powers of 2). When expanding an architecture to a larger word size, an exact multiple of the previous word size does not waste any bits; doubling the word size is the cheapest such multiple. Doubling a power of 2 results in another power of 2. Hence, most microprocessors have word sizes that are powers of 2.

[Note, this questions kind of overlapping with "Why did IBM 7030 or IBM 360 use byte and word addressing simultaneously" , so also consider reading its answer]

Not sure about the exact meaning of your terminology, as every binary word is a power of two, but it feels that you're asking why today it's canon to have a word size being a multiple of a byte. This is simply due the way of unifying word access and byte access, as the IBM 360 did first, by making memory byte addressed.

Also, it's not really about being binary multiples of each, but using a a series of Greatest Common Divisors for all basic data types. The lowest multiple to follow that scheme naturally based on the number two:

• Two bytes give a half word
• Two half word give a word
• Two words give a double word
• and so on ...

For memory usages this brings several major advantages:

• All smaller types can be stored as multiple within any larger type without wasting precious space - think of Russian Matryoshka.

Together with aligned storage (i.e. aligning all types to their natural size)

• Memory interfaces can be made to any type, while guaranteeing that every access to any type of that size or smaller will be done in a single cycle.

• Records can be made by sorting types by decreasing size filling memory without gaps, optimizing storage layout in memory as well as on storage media.

Doing so was a huge step forward in simplifying machine and data structure. Before, with word orientated and word addressed machines, programs were forced to either waste execution time in packing and unpacking smaller types to words, or waste incredible amounts of memory when handling smaller data types - most notably text.

Just think of it, a character on (many) early machines was 6 bit (*1), while a word was 36 bit (*3). To handle a string of text in somewhat econimic way, one had to pack 6 characters into one word, making each character access a pain in the ass (*3), or used each character used a whole word to be stored.

The later would be (*4) outright obscene to any programmer/designer in the 1960s. At that time even mainframes memory size was measured in kilo-words - not mega or giga. Who in his right mind would even think of only using 1/6th thereof?

Lesser obvious, going for the system of stackable sizes also greatly improved the ability to build compatible systems with different memory interface sizes for different requirements, making a the basic design quite adaptable. /360 machiens have been build with memory interfaces from 2 byte (-20) all the way to 128 byte.

Easy to see why the example set by the IBM /360 was copied ever after and became the way memory organisation id done today.

"... and when was that standardized"

Formally never, it simply became a useful self enforcing habit. IBM made the 8 bit byte a standard others had to follow when intending to exchange data - and in the early days all usage of small(er) manufacturers was to carve out a bit of the peripheral business of IBM. It even made DEC go from 12/18/36 bit to 16 bit designs.

8 bit for a byte it was.

With the advent of independent component manufacturers - that is chip makers other than the computer manufacturer itself (*5), the 'mechanic' repeated: Using doubling in each step offers the highest level of reusability and flexibility for components.

Thus when starting to make independent blocks, like TTL and later memory, they were as well most of the time structured as 1-2-4-8, so any computer manufacturer designing a new CPU of his own (which was kind of pointless after the mid 1970s, would have to go rather wasteful ways to leave trail 8/16/32 bit bus width.

Likewise independent CPU manufacturers, think Intel, Motorola, Zilog, etc. will see that the majority of customers will want to use 8 bit bytes, as different byte sizes were a thing of the past. Any system build on that will again follow the rule of using the smallest common multiplier, which two simply is. Thus CPUs became 8/16/32 bit.

After all, common sense is to build what sells most, isn't it?

It's a self enforcing cycle of usefulness

For instance, if I have a 16 bit computer, a 32-bit computer would represent a huge difference in the size of everything. A 20 bit computer or something would be a more incremental increase.

Erm, first question is what you're talking about with these bits?

• Register size?
• (Memory) Word size

By making all of them 20 bit would mean running into the same issue as with 36 bit machines: Either wasting 60% of memory handling of (8-bit) character strings, or adding complex operation for character packing ... and still wasting 20% memory.

Note also, that historical the word size of early machines was usually way larger than their address size. For example a machine as late as a 1959 IBM 7090 had 36 bit words (and registers) but only a 15 bit address size. Likewise the already mentioned standard setting IBM /360, which had byte addressable memory and 32 bit words and registers, but a 24 bit address (*7).

So today's approach of one size fits all, include the equivalence of word size equalling address size is a rather new one (*8).

BTW, looking at your numbers, the 8086 might be the perfect CPU to your idea of 'a more incremental increase'. It's a

• 16 bit CPU (register and word size), with
• 16 bit data bus (allows to fetch a word at once), but
• byte addressing (i.e. smallest generic accessible item) and a
• only needing 16 bit addresses for most operations.

In fact, is this 'incremental' improvement what (IMHO) made the x86 the success it was - a code density comparable to 8 bit CPUs of similar capabilities but an address range far larger than 64 KiB.

*1 - No, Unicode wasn't a thing back then, not even the 7 bit ASCII. It was the 8 bit byte of the /360 that changed it by being able to store everything anyone could ever need from a character set ... well, in 1965 that is.

*2 - Smaller machines were going for 18 bit, still handling the same issue.

*3 - Some machines had bit manipulation instructions to extract bit groups, still, it wasn't the simple `c = *s++;` process of a byte addressable ISA.

*4 - Temporary unpacking excluded.

*5 - In the early days of integrated circuits any computer manufacturer did build their own chips, no matter if IBM or RCA, HP or CDC, Philips or Siemens. In fact, the start of Pure Play independent chip manufacturing, like Fairchild and its Fairchildren, is what enabled the computer revolution of the 1970s. With them, one didn't have to design and manufacture all chips needed for a computer in house, but could focus on designing the machine from existing components.

Kind of what has been repeated in the 2000s, by TMSC and others, enabling fabless production due providing low level buildign blocks (process design kit) and handling all physical manufacturing.

*6 - Might need really deep pockets.

*7 - A step copied by Motorola's 68k a decade later :)

*8 - And when looking close then even the seemingly 64 bit addressing capabilities of a x86-64 turns into 'only' 48 bits maximum virtual address space and a (theoretical) 52 bit physical address space.

• Alternatively, machines would use each word of memory as a "word" in a literal sense, since six 6-bit characters would very nicely hold a FORTRAN identifier. Sep 6, 2022 at 18:58
• @supercat causality was rather the other way around - identifiers (not just FORTRAN) were 6 characters as they could be easy handled as words. Sep 6, 2022 at 19:01
• Was the term "word" used to describe such chunks of storage prior to their usage to hold symbols? The allowable size of the symbols would naturally have been chosen to fit the capacity of machine storage units, but the use of machine storage chunks to hold symbols would make the use of the term "word" quite natural. Sep 6, 2022 at 19:06
• @supercat re 'word'. Yes. See e.g. this 1953 paper on the IBM 701. See page 2 under 'number system'; the source is not amenable to cut'n'paste. Sep 6, 2022 at 21:46
• @another-dave: Thanks for that link. Fascinating stuff. Sep 9, 2022 at 16:27