Some early RISC CPUs had branch delay slots, the theory being that this would make the CPU both cheaper and faster; you could omit some interlock circuitry, and at the same time, in some cases, execute another instruction in what would otherwise have been a wasted cycle. According to https://en.wikipedia.org/wiki/Delay_slot
Branch delay slots are found mainly in DSP architectures and older RISC architectures. MIPS, PA-RISC, ETRAX CRIS, SuperH, and SPARC are RISC architectures that each have a single branch delay slot; PowerPC, ARM, Alpha, and RISC-V do not have any. DSP architectures that each have a single branch delay slot include the VS DSP, μPD77230 and TMS320C3x. The SHARC DSP and MIPS-X use a double branch delay slot; such a processor will execute a pair of instructions following a branch instruction before the branch takes effect. The TMS320C4x uses a triple branch delay slot.
There is nowadays a consensus that it is best to omit such things from an architecture, on the grounds that while they may be helpful in early implementations, later implementations will prefer a larger number, and later still will have branch predictors which means there is no fixed number of delay slots, so it just becomes baggage.
At what point did pipelines become deep enough that, if you were going to design the architecture with delay slots at that time, the number of them to include would've been greater than one? For example, which MIPS CPU first found itself in the position of 'well, if we were going to have delay slots at all, the correct number would've been 2, so the architecturally specified 1 delay slot doesn't actually mean we can omit those interlocks'?